Battery Management Considerations
Ensuring current coming out of the battery is as minimal as possible while the Game Boy is turned off is crucial for long-lasting save data. The higher the current, the lower the battery life! But we need to do this without breaking compatibility with normal operation. So here are the things we need to keep in mind:
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SRAM must have continuous power to retain save data.
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Data on the SRAM must be accessible during normal gameplay.
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The number of battery-powered current-consuming components should be minimized, and those that are powered must use as little current as possible.
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Operation while the voltage is ramping down after turning off the power switch must be restricted to prevent junk data from being written to cartridge RAM.
For most Game Boy games, there were two main sizes of SRAM chips used - 64 Kbit and 256 Kbit (further refered to as just 64K or 256K). The pinouts of these two types of chips are nearly identical:
The big differences are the number of address pins and the number of chip enable pins. The 64K chip has 13 address pins and two chip enables (/CE and CE2), and the 256K chip has 15 address pins and one chip enable (just /CE). The additional address pins on the 256K SRAM gives it more memory, but one of the chip enable pins had to be sacrificed to accommodate this. This is kind of important, because the chip enable pins influence two main things - they tell the chip when data is being accessed, and how much current the chip is drawing during standby. For 64K SRAM chips, that's pretty easy - use one chip enable pin for data access, and the other for data retention mode. But for 256K SRAM, you have to do both of those functions at once. Look at the requirements for the low "data retention current" on the AS6C6264 datasheet and the AS6C62256 datasheet:
For 64K, /CE needs to be at VCC, or CE2 needs to be at GND for the current to be minimized. For 256K, /CE needs to be at VCC, full stop (in this case, VCC is whatever voltage appears on the SRAM's VCC pin, so when power is off that's the battery voltage). That's not super convenient if the power is off - something needs to make the /CE pin go to VCC, which means whatever that something is better not be pulling a lot of current, lest we lower our battery life.
If you use a 256 Kbit SRAM chip, but solder the jumpers on my boards for 64 Kbit, the CE2 pin on the 64 Kbit RAM chip will be continuously enabled by setting it high. And for 1 Mbit SRAM, there's an extra four pins to expand the memory space, and it also restores the CE2 pin that the 64 Kbit SRAM has. For easy implementation, my boards still only use the /CE pin for data access and retention, and keeps the new CE2 pin continuously enabled.
Games that have 64K SRAM can use the MBC5 for controlling the /CE pin for data access, and U4 (the MM chips) for keeping CE2 at GND when power was off. But for 256K SRAM, that CE2 pin isn't available anymore. As an example - for MBC1 games, if a cartridge had an MM1026 chip for battery management, the MBC1 was powered via of the battery as well, and had internal logic to keep /CE logic high when disabled. The MM1026 has a /CE output as well that will pull the output up to the battery voltage, however it does not have a way to allow the /CE pin to be accessed during normal gameplay. So the MBC1 needs to take care of both functions, but since it's powered from the battery when power is off, that means the battery life would be impacted.
Luckily, the /CE pin on 256K SRAM chips can be managed completely by the MM1134. And all MBC5 games used this chip, if it had battery-backed RAM. The MM1026 wasn't used at all, as far as I can tell. Using the MM1134 removed the requirement of keeping the MBC5 powered while the cartridge was off, if using larger than 64K RAM. Handy! But on my custom carts, I add in an extra bit of circuitry to allow you to do this with just an MM1026, or completely new off-the-shelf components without the need for a donor - just in case you have an MBC5 donor that doesn't have RAM on it. But before covering that, let's talk about the other important part of the battery backup system - how to properly and safely manage shifting between console power to battery power.
When you turn the power switch off on a DMG, the voltage on the VCC supply will ramp down. However, the DMG CPU requires 5 V to operate properly. A sufficiently lower voltage supplying the CPU may cause erroneous operation on the I/O pins of the CPU, even for a brief period of time. This can corrupt data stored on the SRAM of the game cartridge, say if the CPU accidentally writes junk data to part of the memory. This is bad!
In order to prevent this problem, Game Boy cartridges that have battery-backed SRAM on them use the battery management chip U4 to shut down operation of the CPU on pin 30 of the cart edge - the /RST (or /RESET) line. Asserting this to GND will stop all operation on the I/O pins, preventing corruption from occurring. On Game Boy carts, /RESET output and CS output pins will be pulled to GND whenever voltage on the VCC pin is below ~4.2V.
Two main revisions of the battery management chip are used on cartridges, and are slightly different - the MM1026 and the MM1134.
The MM1026 is the battery management chip that was used more commonly early on in the Game Boy lifecycle.
Please note that the MM1026 has a /RESET output pin, but this is not the same as the Game Boy CPU /RESET input, the MBC1 /RESET input, or the cart edge /RST pin 30! I will call the MM1026's pin 2 the "Reset output pin" from now on for clarity.
The MM1026 is also used to pull the memory mapper's /RESET input to GND as well. This is more important on boards that powered their MBC chips off of the battery (particularly MBC3) as it greatly reduces power consumption, but it also further prevents any junk data from being written to the SRAM during power-down.
The MM1134 is nearly identical to the MM1026, with one distinct difference that's crucial for OEM MBC5 games. There is one extra input that was previously an unconnected pin on the MM1026 - the /Y input. This input is intended to be used with a RAM /CE signal. It controls the /CS output (pin 5) on the MM1134. See the schematic and timing diagram below:
Essentially, the /CS output will follow the /Y input, unless VCC is below the 4.2V power-off threshold. Then, /CS will be pulled to VOUT (the combination of VCC and VBAT). Hey, this is great, because it means we can control that pesky 256K SRAM /CE pin and put it in a low power state when the power shuts off!
Note: If you ground the /Y input, then the MM1134 will act exactly like an MM1026.
One minor, but important, note that drives a few design choices - there are actually two outputs on the MM1026/MM134 that go low when power is below 4.2 V. One of them is open collector (pin 2, the "Reset output"), and one is instead driven high by an internal transistor or pulled low by an internal pull-down (pin 3, the "CS output"). This is important because it means you cannot safely use the CS output pin to control the Game Boy's /RESET line.
On the DMG, the CPU's /RESET input is also connected to half of the power switch. When the switch is fully turned off, the /RESET input is pulled to GND directly.
[Image adapted from gekkio's DMG CPU board schematic]
This means that to ensure no damage is done to the battery management chip, any output connected to the Game Boy's /RESET input must be open collector. Open collector outputs can either float their output, or (in this case) pull it to GND - reference the "Pin 2 Reset Output" schematic above. That means pulling it to GND with the power switch won't damage anything internal to the chip, it will just safely bypass the pin's function.
But, in the case of pin 3 on the MM chips, the "CS output" pin, imagine a scenario where the power switch was turned off, but the capacitors on the board have not yet discharged down to 0V. This means there'd still be some residual voltage on the VCC net. But, the CS output pin is connected to VCC via the transistor internal to the chip, and if VCC hasn't dropped far enough, then this would still be pulled high to VCC. So if you had connected pin 3 to the /RESET input on the Game Boy, in this scenario, there would be a path from VCC on the MM's supply pin, through the transistor on pin 3, through the power switch on the DMG, to GND - short circuiting the capacitors on the board. This means that for a moment, the internal transistor driving pin 3 would experience a surge of current. Since the output is not designed to do that, it could cause damage to the part. So let's avoid that situation!
In conclusion, any output connected to the /RESET net on the Game Boy must be open collector.
On the GBC, they added a chip that pulls the /RESET line to GND through an open collector output whenever the voltage on VCC drops below 3.5 V, instead of using the power switch to ground the input. If the DMG had this, maybe Nintendo wouldn't have needed these MM chips but could use something a bit simpler. But we must design cartridges with DMG compatibility in mind!
For reference again, here is a pinout diagram of the MM1026 and MM1134.
The VOUT pin is a combination of the VCC and VBAT pins. VCC is connected to the Game Boy's 5V supply, and VBAT is connected to the battery (through a current-limiting resistor). When VCC drops below 3.3V during power-down, the MM chip switches VOUT to be supplied by VBAT instead of VCC. Conversely, when it passes above 3.3V during power-on, the MM chip switches VOUT to be supplied by VCC instead. This guarantees constant power to the SRAM to keep save data retained at all times, assuming the battery is not dead.
Because anything connected to the /RESET input pin on the cart edge must be open collector, the open collector output of the MM chip, pin 2, is connected to the /RESET cart edge pin (pin 30). Generally, the MBC's /RESET input is connected to the driven CS output of the MM chip, pin 3.
The RAM_/CS output of the MBC can be connected to the /Y input (pin 7) of the MM1134, and the /CS output (pin 5) can then be connected to the SRAM /CE input. As explained earlier, the state of the /CS output of the MM1134 is the same as the /Y input, unless VCC is below 4.2V, in which case the /CS output is pulled up to the VOUT voltage to satisfy low-current data retention requirements of the SRAM.
On some carts with the MM1026, Nintendo opted to keep the MBC powered on the battery in order to control the RAM's /CE pin to keep it in low power mode. But this inherently caused a higher current draw from the battery, and thus lower battery life (even if this is somewhat inconsequential - the MBC1 and MBC5 are quite efficient). Because the MM1026 does not have the gated /CS output functionality, if you want to keep the MBC chip off of the battery power, you need to add the function back with some external components. Below is an example of the method I use on the MBC5 carts to do this.
In this schematic, RAM_/CS connects to the MBC5's RAM_/CS output pin, RAM_/CS_G connects to the SRAM's /CE input, and VCC_SRAM connects to the MM1026 VOUT pin.
- When the CS output is driven low (when VCC is below 4.2V), conduction between the drain and source of Q2 will be off; the RAM_/CS_G net will be pulled up to the battery-backed voltage via R7, no matter what RAM_/CS is doing.
- When the CS output is driven high (when VCC is above 4.2V), conduction between the drain and source of Q1 is allowed; RAM_/CS_G will follow the RAM_/CS output, which will allow the MBC5 to control the SRAM /CE input.
Thus, this circuit essentially adds the MM1134's gated /CS output functionality back into the circuit.
If you do not have one of these MM chips, as you can only typically get them from donor Game Boy cartridges and not all games use them, you can achieve the same results using commercially-available components. In order to do so, you can use the TPS3613 - a Texas Instruments chip that is almost identical to the MM1134, with a few minor differences.
Here is the timing diagram from the TPS3613 datasheet, showing the relations between the inputs and outputs of the chip.
Like the MM chips, VOUT is created by VCC or VBAT. But instead of a hard internal threshold, the output of this pin is determined by the voltage on the SENSE pin. If the voltage on SENSE is above an internal set voltage of 1.15 V (shown as VIT in the diagram), VOUT is equivalent to VCC. When the SENSE voltage drops below VIT, and when VCC drops below VBAT, VOUT switches over to being powered by VBAT instead.
The voltage on SENSE is determined by the voltage divider made with R9 and R10. The MM chips have an internal threshold of 4.2 V for determining that the power is going off and the /RESET outputs should be asserted to protect the RAM from spurious writes. So for this design, I'll stick to that threshold.
The /RESET and RESET outputs of the TPS3613 are push-pull. This is slightly inconvenient, because it means you cannot directly connect them to the /RST pin on the cart edge (pin 30), because as discussed earlier, any connection to this pin must be open collector. So, we just have to make it open collector (or in this case, open drain). Adding Q1, an N-channel MOSFET, achieves this.
- When voltage on the SENSE pin is above the internal 1.15V threshold, the /RESET output pin is asserted high allowing the MBC to function, and the RESET output pin is asserted low. This will keep Q1 off and allow /RST, pin 30 on the cart edge, to float.
- When voltage on the SENSE pin drops below the internal 1.15V threshold, the /RESET output pin is asserted low turning off the MBC, and the RESET output pin is asserted high. This will turn Q1 on, and pull pin 30 on the cart edge to GND. Note that the positive RESET output follows the voltage on the VDD pin, so once the 5V supply on the Game Boy depletes, Q1 will be off again.
- If your MBC chip is not powered on the battery, this won't make a difference since there will be no power to the MBC. But if you are using an MBC3 with the RTC function, you need to keep the MBC3 powered on the entire time. In this case, you can use the /CEOUT pin (with /CEIN tied to GND) to act as an alternative to the positive RESET output, as this will remain powered even after VDD is removed.
The /CEIN input and /CEOUT output pins of the TPS3613 act exactly like the /Y input and /CS output pins of the MM1134 - /CEOUT will follow /CEIN as long as the voltage on the SENSE pin is above 1.15V. So the RAM_/CS output is wired similarly to the MM1134 implementation.