[TRTLLM-12154][test] Add Qwen3-32B FP8 disagg stress test by brnguyen2 · Pull Request #14278 · NVIDIA/TensorRT-LLM

brnguyen2 · 2026-05-18T23:21:10Z

Summary

Adds Qwen3-32B FP8 disaggregated serving coverage for the Eagle3 path on 8 GPUs.

The new disagg config uses:

target model: Qwen3/Qwen3-32B-FP8
Eagle3 draft model: Zhi-Create-Qwen3-32B-Eagle3, resolved relative to llm_models_root()
4 context workers with TP1 and 1 generation worker with TP4
FP8 KV cache, chunked prefill, block/partial reuse, and DEFAULT cache transceiver
top-level speculative_config so context and generation workers agree on the cache-state handshake

The disagg harness now resolves relative model and speculative_config.speculative_model values through llm_models_root() while preserving absolute paths. This keeps the YAML portable across CI/local model roots.

Also makes the GSM8K lm-eval parser tolerate padded table cells, matching the output shape emitted by the local-completions run.

Test entries:

test_disaggregated_qwen3_32b_fp8 smoke test in l0_dgx_h200.yml
test_disaggregated_stress_test::qwen3_32b_fp8_stress in qa/llm_function_stress.txt, request_count=10000, accuracy_threshold=0.42

Refs: TRTLLM-12154

Test plan

Targeted smoke test passed before the upstream rebase with FP8 KV + Eagle3
Rebuild on upstream main after rebase
Rerun tests/integration/defs/disaggregated/test_disaggregated.py::test_disaggregated_qwen3_32b_fp8 after rebuild
Locally validated the stress node with temporary request/output/lm-eval limits; aiperf completed 16/16 requests and GSM8K parsed as 0.75 against the 0.42 threshold. Temporary limits are not committed.
Pre-merge CI

Summary by CodeRabbit

Release Notes

Tests
- Added disaggregated test coverage for Qwen3-32B-FP8 model with speculative decoding configuration.
- Improved GSM8K accuracy extraction to support variable whitespace and both integer and decimal values.
- Extended stress test parametrization to include new Qwen3-32B-FP8 test scenarios on H200 GPUs.

brnguyen2 · 2026-05-18T23:21:23Z

/bot run --extra-stage "DGX_H200-8_GPUs-PyTorch-Post-Merge-1"

brnguyen2 · 2026-05-19T13:07:57Z

/bot run --extra-stage "DGX_H200-8_GPUs-PyTorch-Post-Merge-1"

brnguyen2 · 2026-05-19T13:10:38Z

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github-actions · 2026-05-19T13:10:50Z

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tensorrt-cicd · 2026-05-19T13:13:31Z

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brnguyen2 · 2026-05-20T20:49:49Z

/bot run --extra-stage "DGX_H200-8_GPUs-PyTorch-Post-Merge-1"

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brnguyen2 · 2026-05-20T22:00:04Z

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brnguyen2 · 2026-05-21T00:18:54Z

Verified that the targeted rerun reached the newly added test and it passed:

DGX_H200-8_GPUs-PyTorch-Post-Merge-1/disaggregated/test_disaggregated.py::test_disaggregated_qwen3_32b_fp8[Qwen3/Qwen3-32B-FP8]

The selected test run completed successfully with this pytest summary: 16 passed, 12 skipped, 17175 deselected.

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brnguyen2 · 2026-05-22T11:40:57Z

The recent CI failure on this PR (L0_MergeRequest_PR #39365 → L0_Test-x86_64-Single-GPU #2493, stage [DGX_B200-PyTorch-5]) is an unrelated pre-existing regression on main:

Failing test: accuracy/test_llm_api_pytorch.py::TestQwen3_5_35B_A3B::test_bf16_mtp[mtp_on]
Error: AttributeError: 'NoneType' object has no attribute 'gather_ids' at tensorrt_llm/_torch/models/modeling_speculative.py:1748 during autotuner warmup.
Likely introduced by [TRTLLM-12500][feat] Add support for Qwen3.5 VL MoE - REVERTED by #14599 #14164 (Qwen3.5 VL MoE) — Qwen3.5-35B-A3B text MoE is being routed through modeling_qwen3vl.py and spec_metadata is None during the warmup forward.
The mtp_off variant of the same test passes.
Tracked in https://nvbugs/6206179.

This PR only touches the Qwen3-32B FP8 disagg stress test plumbing — none of its files are related to modeling_speculative.py / modeling_qwen3vl.py / autotuner warmup. No upstream commit since 96a4a0937e touches those files, so a rebase doesn't help. The latest commit on this branch (473ba2c) waives the failing test pending an upstream fix.

Failure analysis: https://pbss.s8k.io/v1/AUTH_svc_tensorrt/sw-tensorrt-ci-analysis/LLM/main/L0_MergeRequest_PR/39365/failure_analysis.html

brnguyen2 · 2026-05-22T11:41:01Z

/bot run

brnguyen2 · 2026-05-22T11:42:15Z

/bot kill

brnguyen2 · 2026-05-22T11:42:19Z

/bot run --disable-fail-fast

Add a Qwen3-32B FP8 disaggregated serving smoke and stress test that exercises Eagle3 with 4x TP1 context workers and 1x TP4 generation worker on 8 GPUs. The YAML enables FP8 KV cache, chunked prefill, block and partial reuse, cache transfer, and a top-level Eagle3 speculative_config shared by context and generation workers. The draft model is stored as a model-root-relative path and the disagg harness now resolves relative model and speculative_model values through llm_models_root while preserving absolute paths. Wire the smoke test into the H200 L0 list and the full 10k-request stress case into the QA stress list. Add Qwen-specific output substring checks and keep the stress accuracy threshold aligned with the adjacent GPT-OSS stress case. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>

Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>

…t_bf16_mtp[mtp_on] The test crashes during autotuner warmup with 'NoneType' object has no attribute 'gather_ids' at modeling_speculative.py:1748 when MTP eagle one-model is combined with Qwen3.5-35B-A3B. Pre-existing regression on main introduced by the Qwen3.5 VL MoE landing (96a4a09); unrelated to this PR's changes. Tracked in https://nvbugs/6206179. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>

tensorrt-cicd · 2026-05-22T11:46:38Z

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github-actions Bot assigned brnguyen2 May 18, 2026

brnguyen2 force-pushed the brnguyen/qwen3-32b-fp8-disagg-stress branch from 181a22d to ce5f6a0 Compare May 19, 2026 13:07

brnguyen2 force-pushed the brnguyen/qwen3-32b-fp8-disagg-stress branch 5 times, most recently from c7357ef to e4166bb Compare May 20, 2026 18:55

brnguyen2 force-pushed the brnguyen/qwen3-32b-fp8-disagg-stress branch from e4166bb to 690a201 Compare May 20, 2026 21:10

brnguyen2 force-pushed the brnguyen/qwen3-32b-fp8-disagg-stress branch from 690a201 to 2c22fef Compare May 21, 2026 00:22

brnguyen2 marked this pull request as ready for review May 21, 2026 00:28

brnguyen2 requested a review from a team as a code owner May 21, 2026 00:28

brnguyen2 added 4 commits May 22, 2026 06:46

[TRTLLM-12154][test] Address disagg helper naming nit

aa0ff5d

Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>

[TRTLLM-12154][test] Move model path helper to common

73f28a5

Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>

brnguyen2 force-pushed the brnguyen/qwen3-32b-fp8-disagg-stress branch from 473ba2c to 02a618a Compare May 22, 2026 11:46

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Summary

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