[None][perf] move packed FP8 scale zeroing into kernel#14358
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Signed-off-by: Jin Li <59594262+liji-nv@users.noreply.github.com>
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…_dim_uint32 in kernel The packed-scale kernel previously sized its grid on `m` and assumed `m_aligned == ceil(m/4)*4` to keep the per-row STG in bounds. If a caller passes a `scale_leading_dim_uint32` that's larger than `ceil(m/4)*4` (e.g. TMA padding to a wider alignment), the tail rows `[ceil(m/4)*4, scale_leading_dim_uint32)` are never visited and read back as uninitialized memory. Switch the grid sizing to `ceil(scale_leading_dim_uint32 / WarpsPerBlock)` so the kernel covers the full leading dim of the buffer, and add an `m_idx < scale_leading_dim_uint32` guard on the store to drop the (≤ 3) rows past the buffer when the leading dim isn't a multiple of WarpsPerBlock. Matches @liji-nv's review on NVIDIA#14348 / NVIDIA#14358. Signed-off-by: Mingyang Hao <mingyangh@nvidia.com>
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