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v2.0.2-p0-audit — AERIS-10 Pre-Bringup P0 Audit Closure + FT2232H Timing Relax

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@JJassonn69 JJassonn69 released this 20 Apr 19:42
· 20 commits to main since this release
v2.0.2-p0-audit
ca8c586

AERIS-10 Pre-Bringup P0 Audit Closure + FT2232H Timing Relax

Production bitstream for xc7a50t-ftg256-2 closing the 2026-04-20 pre-bringup P0 audit. Key items: a datasheet-accurate FT2232H output_delay (was synthetically over-constrained by ~8 ns in v2.0.1), 400 MHz CIC/MMCM margin fixes, an ADC overrange hold waiver matching the existing source-synchronous pattern, and an MCU refactor removing the redundant SPI T/R path now that the FPGA chirp controller owns per-chirp switching.

Timing (2026-04-20, commit ca8c586)

Clock Period WNS WHS Failing
clk_mmcm_out0 (400 MHz) 2.5 ns +0.029 +0.080 0
adc_dco_p (400 MHz) 2.5 ns +0.906 — 0
clk_100m 10 ns +0.263 +0.057 0
clk_120m_dac 8.333 ns +1.635 +0.130 0
ft_clkout (60 MHz) 16.667 ns +1.053 +0.121 0
Pulse width (WPWS) — +0.361 — 0

All user-specified timing constraints are met. 0 failing endpoints (setup / hold / pulse width).

Utilization (xc7a50tftg256-2)

Resource Used Available Util%
LUTs 10,358 32,600 31.77%
Flip-Flops 12,905 65,200 19.79%
BRAM tiles 17.5 75 23.33%
DSP48E1 112 120 93.33%
F7 Muxes 2,499 16,300 15.33%
F8 Muxes 661 8,150 8.11%

Reduction vs v2.0.1 (LUT 66.67% → 31.77%, BRAM 74.00% → 23.33%) attributable to P1/P2 audit cleanup (dead module / unused debug path removal). Post-synth hierarchy verified all radar modules instantiated: CFAR, DDC (87 DSP), matched filter (12 DSP, 12 BRAM), Doppler processor (10 DSP, 4 BRAM), MTI canceller, chirp controller.

What Changed (from v2.0.1-reset-fanout)

FPGA — FT2232H Timing Closure (F-0.9 Option B)

  • xc7a50t_ftg256.xdc: output_delay relaxed from synthetic 11.667 ns to datasheet 3.5 ns (FTDI TN_167 t_su); input_delay tightened 9.667 → 10.0 ns (t_co); added explicit -min constraints (+0.5 / −1.0 ns) so hold is now actually analyzed.
  • adc_clk_mmcm.xdc: extended existing adc_d_p[*] source-synchronous hold waiver to include the adc_or_p overrange pin (same IBUFDS→BUFIO topology, same external-PCB-layout argument; audit F-0.1 follow-up).

FPGA — 400 MHz Margin (F-2026-04-20-A/B)

  • cic_decimator_4x_enhanced.v: reset_h max_fanout 50 → 25 for tighter regional replication.
  • adc_clk_mmcm.xdc: BUFIO→BUFG max_delay 2.500 → 2.700 ns to cover IDDR (ILOGIC) → FDRE (SLICE) re-registration route.

MCU — ADAR1000 T/R Ownership Refactor

  • ADAR1000_Manager.{h,cpp}: removed fastTXMode / fastRXMode / pulseTXMode / pulseRXMode / setADTR1107Control / setSwitchSettlingTime / setFastSwitchMode. Per-chirp T/R is owned by plfm_chirp_controller (FPGA) driving adar_tr_x; the SPI RMW path was architecturally redundant, toggled the wrong bit (TR_SOURCE vs TR_SPI), and bundled a datasheet-violating PA+LNA-simultaneously-biased state.
  • main.cpp (executeChirpSequence, runRadarPulseSequence): call sites cleaned up.
  • stm32_hal_mock.{h,c}: CMSIS-Core DWT / CoreDebug / SystemCoreClock stubs so F-4.7's DWT-based delayUs() compiles under host tests.

Build Reproduction

cd 9_Firmware/9_2_FPGA
vivado -mode batch -source scripts/50t/build_50t.tcl 2>&1 | tee build_50t/vivado.log
Assets 6
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