Draft PR: Fix incorrect inline assembly constraints in dcbt prefetch instructions#5828
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Draft PR: Fix incorrect inline assembly constraints in dcbt prefetch instructions#5828amritahs-ibm wants to merge 1 commit into
amritahs-ibm wants to merge 1 commit into
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Corrected the register constraints for the PowerPC dcbt (Data Cache Block Touch) instruction in Power10 kernel implementations. The dcbt instruction has special behavior where if the first operand (RA) is r0, it uses the value 0 instead of the register contents. Therefore, RA must use the "b" constraint (any GPR except r0), while RB can use "r" (any GPR including r0). Changes: - Changed first operand constraint from "r" to "b" to exclude r0 - Changed second operand constraint from "b" to "r" for flexibility This ensures correct prefetch behavior and compliance with PowerPC ISA specifications, preventing potential issues where r0 might be incorrectly used as the base address register. Signed-off-by: Amrita H S <amritahs@linux.vnet.ibm.com>
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Corrected the register constraints for the PowerPC dcbt (Data Cache Block Touch) instruction in Power10 kernel implementations. The dcbt instruction has special behavior where if the first operand (RA) is r0, it uses the value 0 instead of the register contents. Therefore, RA must use the "b" constraint (any GPR except r0), while RB can use "r" (any GPR including r0).
Changes:
This ensures correct prefetch behavior and compliance with PowerPC ISA specifications, preventing potential issues where r0 might be incorrectly used as the base address register.