Shift Register implementation using Verilog HDL with ModelSim simulation and waveform output Shift Register using Verilog
📌 Description
This project implements a shift register using Verilog HDL. The design is simulated using ModelSim, and the waveform output verifies correct shifting of data with clock pulses.
📁 Files Included
- shift_register.v → Design code
- shift_register_tb.v → Testbench
- run.do → Simulation script
- shift_register_output.png → Waveform output
🛠 Tools Used
- Verilog HDL
- ModelSim
⚙️ Working
- Data is given as input
- On each clock pulse, bits shift to next position
- Output is verified using waveform
📷 Output Waveform
"Output" (shift_register_output.png)
🎯 Conclusion
The shift register is successfully designed and verified using simulation.