opt: circuit(CloClz, LT and ShiftRight)

[eigmax]

Summary

• optimize(CloClz): Remove 5 witness columns (22 → 17, −23%):

  • sr1: Word<T> (4 cols) — hardcode [1, 0, 0, 0] in send_alu since
    sr1 == 1 is always verified.
  • is_clo (1 col) — derive as is_real - is_clz with a single
    when(is_clz).assert_one(is_real) guard.

• optimize(Lt): Remove 4 dead columns byte_equality_check: [T; 4] (35
  → 31, −11%). The field was declared but never referenced in Air::eval or
  trace generation.

• optimize(ShiftRight): Remove 4 redundant columns a: Word<T> (73 →
  69, −5%). Since a[i] == bit_shift_result[i] always holds, pass
  bit_shift_result[0..4] directly to receive_instruction.

Column savings

Chip	Before	After	Saved
CloClz	22	17	5 (−23%)
Lt	35	31	4 (−11%)
ShiftRight	73	69	4 (−5%)
Total			13 columns