Support table

doc/index.rst

@@ -24,5 +24,4 @@ PyFPGA Documentation
    advanced
    tools
    api
-   helpers
    dev

doc/intro.rst

@@ -3,10 +3,6 @@
 Introduction
 ############
 
-
-Detailed support
-----------------
-
 .. ATTENTION::
 
   PyFPGA assumes that the backend Tool is ready to run.
@@ -18,8 +14,74 @@ Detailed support
   * GNU/Linux: extra packages installed, environment variables assigned
     and permissions granted on devices (to transfer the bitstream).
 
+Detailed support
+----------------
+
++------------------------------+---------+----------+------------+-----------+----------+
+|                              | ISE     | Libero   | Openflow   | Quartus   | Vivado   |
++==============================+=========+==========+============+===========+==========+
+|**add_files**                 |         |          |            |           |          |
++------------------------------+---------+----------+------------+-----------+----------+
+|``vhdl``                      | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``verilog``                   | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``system_verilog``            | ``TBD`` | ``TBD``  | ``TBD``    | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``constraint``                | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``block_design``              | ``NY``  | ``NY``   | ``NY``     | ``NY``    | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**set_param**                 |         |          |            |           |          |
++------------------------------+---------+----------+------------+-----------+----------+
+|``boolean`` (*VHDL/Verilog*)  | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``integer`` (*VHDL/Verilog*)  | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``string`` (*VHDL/Verilog*)   | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``real`` (*VHDL/Verilog*)     | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``std_logic`` (*VHDL*)        | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``std_logic_vector`` (*VHDL*) | ``TBD`` | ``TBD``  |``TBD``     | ``TBD``   | ``TBD``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**add_path**                  | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**set_define** (*Verilog*)    | ``TBI`` | ``TBI``  | ``TBI``    | ``TBI``   | ``TBI``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**set_arch** (*VHDL*)         | ``TBI`` | ``TBI``  | ``TBI``    | ``TBI``   | ``TBI``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**generate**                  |         |          |            |           |          |
++------------------------------+---------+----------+------------+-----------+----------+
+|``prj``                       | ``Yes`` | ``Yes``  | ``No``     | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``syn``                       | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``imp``                       | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``bit``                       | ``Yes`` | ``Yes``  | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|**transfer**                  |         |          |            |           |          |
++------------------------------+---------+----------+------------+-----------+----------+
+|``fpga``                      | ``Yes`` | ``NY``   | ``Yes``    | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``spi``                       | ``Yes`` | ``NY``   | ``NY``     | ``NY``    | ``NY``   |
++------------------------------+---------+----------+------------+-----------+----------+
+|``bpi``                       | ``Yes`` | ``NY``   | ``NY``     | ``NY``    | ``NY``   |
++------------------------------+---------+----------+------------+-----------+----------+
+|``detect``                    | ``Yes`` | ``NY``   | ``NY``     | ``Yes``   | ``Yes``  |
++------------------------------+---------+----------+------------+-----------+----------+
+|``unlock``                    | ``Yes`` | ``No``   | ``No``     | ``No``    | ``No``   |
++------------------------------+---------+----------+------------+-----------+----------+
+
+* ``Yes``: already supported
+* ``No``: no plans (or unneeded)
+* ``NY``: Not yet, but maybe someday
+* ``TBD``: To Be Defined
+* ``TBI``: To Be Implemented
+
 Next Steps
 ----------
 
-From here, you can read the :ref:`basic` and :ref:`advanced` sections, check
-the detailed :ref:`api` or start with the available :repo:`Examples <examples>`.
+You can read the :ref:`basic` and :ref:`advanced` sections, check the detailed :ref:`api` or start with the available :repo:`Examples <examples>`.

fpga/project.py

@@ -1,6 +1,6 @@
 #
+# Copyright (C) 2019-2021 Rodrigo A. Melo
 # Copyright (C) 2019-2020 INTI
-# Copyright (C) 2019-2020 Rodrigo A. Melo
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -169,16 +169,18 @@ def add_files(self, pathname, filetype=None, library=None, options=None):
 
         :param pathname: a relative path to a file, which can contain
          shell-style wildcards (glob compliant)
-        :param filetype: the valid values are **verilog** or **vhdl**,
-         **constraint** and **design** (for a graphical block design). It is
-         automatically discovered (based on the extension) if None provided
-         (except for **design**). The default (autodiscovery failed) is
-         **constraint**
+        :param filetype: specifies the file type
         :param library: an optional VHDL library name
         :param options: to be provided to the underlying tool
         :raises FileNotFoundError: when a file specified as pathname is not
          found
-        :raises ValueError: when filetype is unsupported
+        :raises ValueError: when *filetype* is unsupported
+
+        .. note:: Valid values for *filetype* are ``vhdl``, ``verilog``,
+        ``system_verilog``, ``constraint`` (default) and ``block_design``
+        (only **Vivado** is currently supported). If None provided, this
+        value is automatically discovered based on the extension (
+        ``.vhd`` or ``.vhdl``, ``.v`` and ``.sv``).
         """
         pathname = os.path.join(self._absdir, pathname)
         pathname = os.path.normpath(pathname)