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Fix Tcl paths for windows #20

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Merged
rodrigomelo9 merged 3 commits into from
Feb 19, 2021
Merged

Fix Tcl paths for windows #20

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f96bd2b
fix path error on windows
motty-mio2 Feb 19, 2021
796cbd4
Merge pull request #19 from motty-mio2/windows_path
rodrigomelo9 Feb 19, 2021
6812029
fpga: moved fix for Tcl paths in windows from project.py to tools
rodrigomelo9 Feb 19, 2021
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21 changes: 13 additions & 8 deletions fpga/tool/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,11 @@ def run(command, capture):
return result.stdout


def tcl_path(path):
"""Returns a Tcl suitable path."""
return path.replace(os.path.sep, "/")


class Tool:
"""Tool interface.

Expand Down Expand Up @@ -161,20 +166,20 @@ def _create_gen_script(self, tasks):
files.append(' fpga_file {}.edif'.format(self.project))
else:
for path in self.paths:
files.append(' fpga_include {}'.format(path))
files.append(' fpga_include {}'.format(tcl_path(path)))
for file in self.files['verilog']:
files.append(' fpga_file {}'.format(file[0]))
files.append(' fpga_file {}'.format(tcl_path(file[0])))
for file in self.files['vhdl']:
if file[1] is None:
files.append(' fpga_file {}'.format(file[0]))
files.append(' fpga_file {}'.format(tcl_path(file[0])))
else:
files.append(
' fpga_file {} {}'.format(file[0], file[1])
)
files.append(' fpga_file {} {}'.format(
tcl_path(file[0]), file[1]
))
for file in self.files['design']:
files.append(' fpga_design {}'.format(file[0]))
files.append(' fpga_design {}'.format(tcl_path(file[0])))
for file in self.files['constraint']:
files.append(' fpga_file {}'.format(file[0]))
files.append(' fpga_file {}'.format(tcl_path(file[0])))
# Parameters
params = []
for param in self.params:
Expand Down