Support case statement in function.

[fukatani]

Hi shtaxxx-san,
I noticed Pyverilog fail to analyze verilog code as follows (case statement is written in function).

  function func1;
    input in1;
    input sel;
    case(sel)
        'h0:
          func1 = in1;
        default:
          func1 = 1'b0;
    endcase
  endfunction

So first, I modified Bindvisitor._case change to same implementation with Signalvisitor._case.
But by only this change, case statement is not analyzed correctly.

I found that Bindvisitor.getCondlist and Bindvisitor.getFlowlist doesn't work correctly for functioncall and match_flowlist became blank. So in the following lines, tree is added in the unexpected form.

'tree = reorder.reorder(
self.appendBranchTree(current_tree, match_flowlist, add_tree))'

So I commented out 'if frame.isFunctioncall(): break' in Bindvisitor.getCondlist and Bindvisitor.getFlowlist.

Under this modification, match_flowlist is valid (not blank), and added tree in correct form.

But in honest, I don't understand why this line was inserted, and it can be deleted.
Please give me advise if there are other good correction method.

With this modification, analysis result of testcode/function.v was changed. (I think previous analysis result is not correct.)

[shtaxxx]

Thank you for you contribution.

I think the first modification in _case() method is fine and a natural correction.

Unfortunately, I don't remember why I inserted "if frame.isFunctioncall(): break" in getCondlist and getFlowlist methods, because these parts had been implemented about 3 years ago.

Since your modification seems to improve analysis results, I should merge your pull request at this time, even I cannot remember the reason.

Thanks.

[fukatani]

Thank you for your merging.
I'm going to add the testcases about function call in near future.

Anyway, reliability of Pyverilog seems to be greatly improved by a series of retouching in recent.
Current pyverilog can pass on the project of ten thousands of lines of ASIC.