Support case statement in function.

pyverilog/dataflow/bindvisitor.py

@@ -362,18 +362,27 @@ def visit_CaseStatement(self, node):
         start_frame = self.frames.getCurrent()
         caseframes = []
         self._case(node.comp, node.caselist, caseframes)
+        #self._case(node.comp, tuple(reversed(list(node.caselist))), caseframes)
         self.frames.setCurrent(start_frame)
         for f in caseframes:
             self.copyBlockingAssigns(f, start_frame)
 
     def visit_CasexStatement(self, node):
         return self.visit_CaseStatement(node)
-        
+
     def _case(self, comp, caselist, myframes):
         if len(caselist) == 0: return
 
         case = caselist[0]
-        cond = Eq(comp, case)
+        cond = IntConst('1')
+        if case.cond is not None:
+            if len(case.cond) > 1:
+                cond = Eq(comp, case.cond[0])
+                for c in case.cond[1:]:
+                    cond = Lor(cond, Eq(comp, c))
+            else:
+                cond = Eq(comp, case.cond[0])
+        #else: raise Exception
         label = self.labels.get( self.frames.getLabelKey('if') )
         current = self.stackNextFrame(label, 'if',
                                       frametype='ifthen',
@@ -919,7 +928,7 @@ def getCondlist(self, scope):
             if cond is not None:
                 ret.append(self.makeDFTree(cond, self.reduceIfScope(s)))
             if frame.isModule(): break
-            if frame.isFunctioncall(): break
+            #if frame.isFunctioncall(): break
             s = frame.previous
         ret.reverse()
         return tuple(ret)
@@ -932,7 +941,7 @@ def getFlowlist(self, scope):
             cond = frame.getCondition()
             if cond is not None: ret.append(not frame.isIfelse())
             if frame.isModule(): break
-            if frame.isFunctioncall(): break
+            #if frame.isFunctioncall(): break
             s = frame.previous
         ret.reverse()
         return tuple(ret)

testcode/case_in_func.v

@@ -0,0 +1,32 @@
+module TOP(IN1,SEL);
+  input IN1,SEL;
+  reg bit;
+
+
+  always @* begin
+      bit <= func1(IN1,SEL);
+  end
+
+  function func1;
+    input in1;
+    input sel;
+    case(sel)
+        'h0:
+          func1 = in1;
+        default:
+          func1 = 1'b0;
+    endcase
+  endfunction
+
+/*
+  always @* begin
+    case(SEL)
+        'h0:
+          bit = IN1;
+        default:
+          bit = 1'b0;
+    endcase
+  end
+*/
+
+endmodule

tests/dataflow_test/test_case_in_func.py

@@ -0,0 +1,61 @@
+import os
+import sys
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
+from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
+codedir = '../../testcode/'
+
+expected = """\
+TOP.SEL: TOP_SEL
+TOP.md_always0.al_block0.al_functioncall0.in1: TOP_IN1
+TOP.md_always0.al_block0.al_functioncall0._rn1_func1: 1'd0
+TOP.bit: (((TOP_SEL=='d0))? TOP_IN1 : 1'd0)
+TOP.md_always0.al_block0.al_functioncall0.func1: (((TOP_SEL=='d0))? TOP_IN1 : 1'd0)
+TOP.md_always0.al_block0.al_functioncall0.sel: TOP_SEL
+TOP.md_always0.al_block0.al_functioncall0._rn0_func1: TOP_IN1
+TOP.IN1: TOP_IN1
+"""
+
+def test():
+    filelist = [codedir + 'case_in_func.v']
+    topmodule = 'TOP'
+    noreorder = False
+    nobind = False
+    include = None
+    define = None
+
+    analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
+                                       noreorder=noreorder,
+                                       nobind=nobind,
+                                       preprocess_include=include,
+                                       preprocess_define=define)
+    analyzer.generate()
+
+    directives = analyzer.get_directives()
+    instances = analyzer.getInstances()
+    terms = analyzer.getTerms()
+    binddict = analyzer.getBinddict()
+
+    optimizer = VerilogDataflowOptimizer(terms, binddict)
+    optimizer.resolveConstant()
+
+    c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
+                                            binddict,
+                                            resolved_terms=optimizer.getResolvedTerms(),
+                                            resolved_binddict=optimizer.getResolvedBinddict(),
+                                            constlist=optimizer.getConstlist()
+                                            )
+
+    output = []
+    for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x[0])):
+        tree = c_analyzer.makeTree(tk)
+        output.append(str(tk) + ': ' + tree.tocode())
+
+    rslt = '\n'.join(output) + '\n'
+
+    print(rslt)
+    assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()

tests/dataflow_test/test_func.py

@@ -0,0 +1,60 @@
+import os
+import sys
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
+from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
+codedir = '../../testcode/'
+
+expected = """\
+TOP.RST_X: TOP_RST_X
+TOP.md_always0.al_block0.al_if0_ELSE.al_block2.al_functioncall0.inc: (((!TOP_RST_X))? TOP_al_block0_al_block2_al_functioncall0_inc : (((!TOP_RST_X))? (((&TOP_al_block0_al_block2_al_functioncall0_inc))? 'd0 : (((!TOP_RST_X))? (TOP_al_block0_al_block2_al_functioncall0_inc+'d1) : (TOP_cnt+'d1))) : (((&TOP_al_block0_al_block2_al_functioncall0_inc))? (((!TOP_RST_X))? (TOP_al_block0_al_block2_al_functioncall0_inc+'d1) : (TOP_cnt+'d1)) : (((!TOP_RST_X))? (((&(TOP_al_block0_al_block2_al_functioncall0_inc+'d1)))? 'd0 : (((!TOP_RST_X))? (TOP_al_block0_al_block2_al_functioncall0_inc+'d1) : (TOP_cnt+'d1))) : (((&(TOP_cnt+'d1)))? 'd0 : (((!TOP_RST_X))? (TOP_al_block0_al_block2_al_functioncall0_inc+'d1) : (TOP_cnt+'d1)))))))
+TOP.md_always0.al_block0.al_if0_ELSE.al_block2.al_functioncall0._rn1_inc: (((!TOP_RST_X))? (TOP_al_block0_al_block2_al_functioncall0__rn1_inc+'d1) : (TOP_cnt+'d1))
+TOP.cnt: (((!TOP_RST_X))? 'd0 : (((!TOP_RST_X))? TOP_cnt : (((&TOP_al_block0_al_block2_al_functioncall0_inc))? 'd0 : (((!TOP_RST_X))? (TOP_cnt+'d1) : (TOP_cnt+'d1)))))
+TOP.md_always0.al_block0.al_if0_ELSE.al_block2.al_functioncall0.in: (((!TOP_RST_X))? TOP_al_block0_al_block2_al_functioncall0_in : TOP_cnt)
+TOP.CLK: TOP_CLK
+TOP.md_always0.al_block0.al_if0_ELSE.al_block2.al_functioncall0._rn0_inc: 'd0
+"""
+
+def test():
+    filelist = [codedir + 'function.v']
+    topmodule = 'TOP'
+    noreorder = False
+    nobind = False
+    include = None
+    define = None
+
+    analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
+                                       noreorder=noreorder,
+                                       nobind=nobind,
+                                       preprocess_include=include,
+                                       preprocess_define=define)
+    analyzer.generate()
+
+    directives = analyzer.get_directives()
+    instances = analyzer.getInstances()
+    terms = analyzer.getTerms()
+    binddict = analyzer.getBinddict()
+
+    optimizer = VerilogDataflowOptimizer(terms, binddict)
+    optimizer.resolveConstant()
+
+    c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
+                                            binddict,
+                                            resolved_terms=optimizer.getResolvedTerms(),
+                                            resolved_binddict=optimizer.getResolvedBinddict(),
+                                            constlist=optimizer.getConstlist()
+                                            )
+
+    output = []
+    for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x[0])):
+        tree = c_analyzer.makeTree(tk)
+        output.append(str(tk) + ': ' + tree.tocode())
+
+    rslt = '\n'.join(output) + '\n'
+
+    print(rslt)
+    assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()