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F8 fmha ASM gfx950 #2911

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Merged
JohnNikolay84 merged 8 commits into from
May 7, 2026
Merged

F8 fmha ASM gfx950 #2911

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3e8a0e8
mla with hd128
Apr 24, 2026
8076e52
Fix GPU fault
Apr 24, 2026
8d28651
Fix register clobbing bug in s_load
Apr 24, 2026
92dd9be
Fix a bug in group causal attention kernel
Apr 24, 2026
3e986dd
Fix GPU fault
Apr 27, 2026
0e3d32a
Remove broken varlen variants
May 6, 2026
3a4b0e8
Route FP8 varlen MHA on gfx950 to CK; ASM group will land later
May 6, 2026
425b2aa
Reintroduce group mode kernels
May 6, 2026
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14 changes: 12 additions & 2 deletions aiter/ops/mha.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1293,7 +1293,7 @@ def _flash_attn_forward(
swa = (window_size_left > 0) or (window_size_right > 0)

def is_fmha_v3_fp8():
ret = get_gfx() == "gfx942"
ret = get_gfx() in ("gfx942", "gfx950")
ret = ret and (hdim_q == 128)
ret = ret and (q.dtype == dtypes.fp8)
ret = ret and (
Expand All @@ -1319,6 +1319,11 @@ def can_impl_fmha_v3_fwd():
ret = ret and (not swa)
ret = ret and (q.dtype == dtypes.bf16 or is_fmha_v3_fp8())
ret = ret and (cu_seqlens_q is None and cu_seqlens_kv is None)
# FP8 ASM kernels assemble the GQA-shift from a fixed log2 table
# (1,2,4,8,16); arbitrary divisor ratios route to CK.
if is_fmha_v3_fp8():
gqa_ratio = nhead_q // nhead_k
ret = ret and ((gqa_ratio & (gqa_ratio - 1)) == 0)
return ret

q, k, v = [maybe_contiguous(x) for x in (q, k, v)]
Expand Down Expand Up @@ -2074,7 +2079,7 @@ def _flash_attn_varlen_forward(
swa = (window_size_left > 0) or (window_size_right > 0)

def is_fmha_v3_fp8():
ret = get_gfx() == "gfx942"
ret = get_gfx() in ("gfx942", "gfx950")
ret = ret and (hdim_q == 128)
ret = ret and (q.dtype == dtypes.fp8)
ret = ret and (
Expand All @@ -2100,6 +2105,11 @@ def can_impl_fmha_v3_fwd():
ret = ret and (not swa)
ret = ret and (q.dtype == dtypes.bf16 or is_fmha_v3_fp8())
ret = ret and logits_soft_cap == 0.0
# FP8 ASM kernels assemble the GQA-shift from a fixed log2 table
# (1,2,4,8,16); arbitrary divisor ratios route to CK.
if is_fmha_v3_fp8():
gqa_ratio = nhead_q // nhead_k
ret = ret and ((gqa_ratio & (gqa_ratio - 1)) == 0)
return ret

q, k, v = [maybe_contiguous(x) for x in (q, k, v)]
Expand Down
4 changes: 4 additions & 0 deletions csrc/cpp_itfs/mha_fwd.cu
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Expand Up @@ -183,6 +183,10 @@ std::tuple<int, int, int> get_grid_dim(const mha_fwd_args& a, int ts_qo, const s
{
tg_div = 1; // do not merge the head and tail in seqlen_q direction
}
if(arch_id == "gfx950")
{
tg_div = 1; // v2 asm kernel processes one Q tile per workgroup
}
// batch
int gdx = ((a.seqlen_q + ts_qo - 1) / ts_qo + tg_div - 1) / tg_div;
int gdy = a.nhead_q;
Expand Down
6 changes: 5 additions & 1 deletion hsa/gfx950/fmha_v3_fwd/fmha_fwd.csv
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Expand Up @@ -6,4 +6,8 @@ bf16,128,128,2,1,0,256,64,_ZN5aiter32fmha_fwd_hd128_bf16_causal_groupE,fwd_hd128
bf16,192,128,0,0,0,128,128,_ZN5aiter25fmha_fwd_hd192_hd128_bf16E,fwd_hd192_hd128_bf16.co
bf16,192,128,2,0,0,128,128,_ZN5aiter32fmha_fwd_hd192_hd128_bf16_causalE,fwd_hd192_hd128_bf16_causal.co
bf16,192,128,0,1,0,128,128,_ZN5aiter31fmha_fwd_hd192_hd128_bf16_groupE,fwd_hd192_hd128_bf16_group.co
bf16,192,128,2,1,0,128,128,_ZN5aiter38fmha_fwd_hd192_hd128_bf16_causal_groupE,fwd_hd192_hd128_bf16_causal_group.co
bf16,192,128,2,1,0,128,128,_ZN5aiter38fmha_fwd_hd192_hd128_bf16_causal_groupE,fwd_hd192_hd128_bf16_causal_group.co
fp8bf16,128,128,0,0,0,256,128,_ZN5aiter24fmha_fwd_hd128_fp8_gfx950E,fwd_hd128_fp8.co
fp8bf16,128,128,2,0,0,256,128,_ZN5aiter31fmha_fwd_hd128_fp8_causal_gfx950E,fwd_hd128_fp8_causal.co
fp8bf16,128,128,0,1,0,256,128,_ZN5aiter30fmha_fwd_hd128_fp8_group_gfx950E,fwd_hd128_fp8_group.co
fp8bf16,128,128,2,1,0,256,128,_ZN5aiter37fmha_fwd_hd128_fp8_causal_group_gfx950E,fwd_hd128_fp8_causal_group.co
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