SWDEV-512613 - Enable atomicMin/Max tests #604
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Also part of SWDEV-510994. Enable atomicMin/Max tests. Change-Id: Iacfdc1bc13e8da2f5df8751bb315b37d33cea667
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Stress test failed: |
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Atomic testcases failed in stress testing of Linux PSDB# 10 on MI100, MI200: SWDEV-534815, SWDEV-534812 |
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Unit_Device__hip_check_VGPRs failed in stress testing of Linux PSDB# 1312 on MI200, MI300, Navi31, Navi33 & Navi44 : SWDEV-544007, SWDEV-544010, SWDEV-545066 |
The failure in Unit_Device__hip_check_VGPRs is due to the latest change in llvm. I will add you into chat group. |
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Sorry, I was supposed to update in https://github.com/AMD-ROCm-Internal/hip-tests/pull/5 for Unit_Device__hip_check_VGPRs but wrongly I put comment here. |
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Imported to ROCm/rocm-systems |
(#604) This is to prevent calling catch2 macros from outside catch2 TEST_CASE that can lead to undefined bahavior. This change also disables hipGetProcAddress tests that are not supported on static build. Co-authored-by: Ioannis Assiouras <Ioannis.Assiouras@amd.com> [rocm-systems] ROCm/rocm-systems#604 (commit 605be4b)
This is to prevent calling catch2 macros from outside catch2 TEST_CASE that can lead to undefined bahavior. This change also disables hipGetProcAddress tests that are not supported on static build. Co-authored-by: Ioannis Assiouras <Ioannis.Assiouras@amd.com>
Also part of SWDEV-510994.
Enable atomicMin/Max tests.
Add hipDeviceSynchronize() in TestCore() to make sure kernels are finished in streams before memory copy.
Change-Id: Iacfdc1bc13e8da2f5df8751bb315b37d33cea667