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[AMDGPU][WaveTransform] Separating SiOptimizeExecMaskingPreRA pass usage for both pipelines. #422

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Merged
merged 2 commits into from
Oct 29, 2025
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[AMDGPU][WaveTransform] Separating SiOptimizeExecMaskingPreRA pass usage for both pipelines. #422

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88a20df
[AMDGPU][WaveTransform] Separating SiOptimizeExecMaskingPreRA pass for
vg0204 Oct 29, 2025
997dedf
Addressesd the reviewed feedback in AMDGPUTargetMachine.cpp
vg0204 Oct 29, 2025
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10 changes: 7 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1675,6 +1675,9 @@ void GCNPassConfig::addOptimizedRegAlloc() {
// instructions that cause scheduling barriers.
insertPass(&MachineSchedulerID, &SIWholeQuadModeID);

if (!LateWaveTransform && OptExecMaskPreRA)
insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);

// This is not an essential optimization and it has a noticeable impact on
// compilation time, so we only enable it from O2.
if (TM->getOptLevel() > CodeGenOptLevel::Less)
Expand Down Expand Up @@ -1853,13 +1856,14 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
// allocations.
// addPass(&AMDGPUUpdateAllocatedVGPRLiveRangesID);

// Optimize EXEC-mask related instructions around SGPR register class.
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Can you schedule this before the RegisterCoalescer pass, one line above? The coalescer is a prepare for the next SGPR allocation pass. So don't schedule any pass in between.

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Sure!

if (OptExecMaskPreRA)
addPass(&SIOptimizeExecMaskingPreRAID);

// Now we can perform register-coalescing on remaining copies,
// mainly sgpr copies and wwm-vgpr copies.
addPass(&RegisterCoalescerID);
}

if (OptExecMaskPreRA)
addPass(&SIOptimizeExecMaskingPreRAID);

addPass(createSGPRAllocPass(true));

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/WaveTransform/wave-transform-llc-pipeline.ll
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Expand Up @@ -385,9 +385,9 @@
; GCN-O3-NEXT: AMDGPU Control Flow Wave Transform
; GCN-O3-NEXT: Slot index numbering
; GCN-O3-NEXT: Live Interval Analysis
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: Machine Natural Loop Construction
; GCN-O3-NEXT: Register Coalescer
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: Machine Block Frequency Analysis
; GCN-O3-NEXT: Debug Variable Analysis
; GCN-O3-NEXT: Live Stack Slot Analysis
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -352,8 +352,8 @@
; GCN-O1-NEXT: Rewrite Partial Register Uses
; GCN-O1-NEXT: Machine Instruction Scheduler
; GCN-O1-NEXT: SI Whole Quad Mode
; GCN-O1-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-NEXT: Machine Natural Loop Construction
; GCN-O1-NEXT: Machine Block Frequency Analysis
; GCN-O1-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -665,8 +665,8 @@
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-OPTS-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction
; GCN-O1-OPTS-NEXT: Machine Block Frequency Analysis
; GCN-O1-OPTS-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -983,9 +983,9 @@
; GCN-O2-NEXT: Machine Instruction Scheduler
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
; GCN-O2-NEXT: SI Whole Quad Mode
; GCN-O2-NEXT: SI optimize exec mask operations pre-RA
; GCN-O2-NEXT: SI Form memory clauses
; GCN-O2-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O2-NEXT: SI optimize exec mask operations pre-RA
; GCN-O2-NEXT: Machine Natural Loop Construction
; GCN-O2-NEXT: Machine Block Frequency Analysis
; GCN-O2-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -1315,9 +1315,9 @@
; GCN-O3-NEXT: Machine Instruction Scheduler
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
; GCN-O3-NEXT: SI Whole Quad Mode
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: SI Form memory clauses
; GCN-O3-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: Machine Natural Loop Construction
; GCN-O3-NEXT: Machine Block Frequency Analysis
; GCN-O3-NEXT: Debug Variable Analysis
Expand Down