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This PR adds `__builtin_operator_new` and `__builtin_operator_delete`. The implementation is taken from clang code gen.
The CMake [`set()`](https://cmake.org/cmake/help/latest/command/set.html) command does not accept a conditional expression as a value. As a result, AFFECTED_BY_SWIG_BUG was being set to a string representation of the condition rather than a boolean value, causing it to always evaluate as truthy in subsequent if-checks.
This test does not actually need to use the clang driver. Using the driver means that the environment plays much more into the tests results. We ran into a situation where the driver decided not to pass -fopenmp to the cc1 invocation, causing the test to fail. This also makes the test more consistent with the other OpenMP tests and should make it slightly faster (no subprocess invocation).
Co-authored-by: Aiden Grossman <agrossman154@yahoo.com>
Fix VPlan SLP check incorrectly bailing out for non-VPInstructions. Starting from the beginning of the block will include canonical IVs, which in turn are not VPInstructions. If we hit a non-VPInstruction, we should conservatively treat is as potentially unvectorizable. To keep the tests working as expected, refine mayRead/WriteFromMemory for Load and GEP VPInstructions.
e5edb51 attempted to port this, but seemed to miss a couple things that still showed up on CI. This patch fixes up the missing pieces.
llvm#167060)" (llvm#169238) This reverts commit a52e1af. That commit reverted a change (making isExpandedFromMacro take a std::string) that was explicitly added to avoid lifetime issues. We ran into issues with some internal matchers due to this, and it probably is not an uncommon downstream use case. This patch restroes the original functionality and adds a test to ensure that the functionality is preserved. https://reviews.llvm.org/D90303 contains more discussion.
…vm#164768) Background: X86 APX feature adds 16 registers within the same 64-bit mode. PR llvm#164638 is trying to extend such registers for FASTCC. However, a blocker issue is calling convention cannot be changeable with or without a feature. The solution is to disable FASTCC if APX is not ready. This is an NFC change to the final code generation, becasue X86 doesn't define an alternative ABI for FASTCC in 64-bit mode. We can solve the potential compatibility issue of llvm#164638 with this patch.
…Reg (llvm#168661)" (llvm#169219) Reland d5f3ab8, fix testcases.
…169260) This supposes to fix LLVM Buildbot failures after llvm#164768. I don't have the environment to verify though.
…lvm#169262) Interfaces can be optional: whether an op implements an interface or not can depend on the state of the operation. ``` // An optional code block for adding additional "classof" logic. This can // be used to better enable "optional" interfaces, where an entity only // implements the interface if some dynamic characteristic holds. // `$_attr`/`$_op`/`$_type` may be used to refer to an instance of the // interface instance being checked. code extraClassOf = ""; ``` The current `Pass::canScheduleOn(RegisteredOperationName)` is insufficient. This commit adds an additional overload to inspect `Operation *`. This commit fixes a crash when scheduling an `InterfacePass` for an optional interface on an operation that does not actually implement the interface. This is a re-upload of llvm#168499, which was reverted.
SPIR/SPIR-V are generic targets. Assume they support __bf16.
…llvm#169227) Merge the SkipBits!=0 handling into the first iteration of the word loop. This is the same code structure used by BitVector::find_first_in.
…lvm#169256) I've tested this locally, and the builtins build proceeds without a hitch for m68k-none-none. This is part of a larger effort to establish a working m68k baremetal toolchain.
Fixes a bug in `AMDGPUISelLowering` where alias analysis info is not propagated to split loads and stores. This is required for llvm#161375 --------- Co-authored-by: Leon Clark <leoclark@amd.com>
The motivation for this is that it would be useful to express a
vslideup/vslidedown in a target independent way e.g. from the loop
vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to
poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison,
slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of
the vs2s being poison. We can optimize this away so that we are just
left with a single slideup/slidedown.
…er (llvm#168836) Two years ago, `operand_segment_sizes` and `result_segment_sizes` were renamed to `operandSegmentSizes` and `resultSegmentSizes` (check related commits, e.g. llvm@363b655). However, the op verifiers in IRDL loading phase is still using old attributes like `operand_segment_sizes` and `result_segment_sizes`, which causes some conflict, e.g. it is not compatible with the OpView builder in MLIR python bindings (which generates camelCase segment attributes). This PR is to support to use camelCase segment size attributes in IRDL verifier. Note that support of `operand_segment_sizes` and `result_segment_sizes` is dropped. I found this issue since I'm working on a new IRDL wrapper in the MLIR python bindings.
Collaborator
dpalermo
approved these changes
Nov 24, 2025
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