kconfig: fix kernel-mode FPU support#11
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Now that GENERIC_CPU_DEVICES calls arch_register_cpu(), which can be overridden by the arch code, switch over to this to allow common code to choose when the register_cpu() call is made. This allows topology_init() to be removed. This is an intermediate step to the logic being moved to drivers/acpi, where GENERIC_CPU_DEVICES will do the work when booting with acpi=off. This patch also has the effect of moving the registration of CPUs from subsys to driver core initialisation, prior to any initcalls running. Signed-off-by: James Morse <james.morse@arm.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/E1r5R4G-00Ct0M-PS@rmk-PC.armlinux.org.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: liwei <liwei728@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Convert riscv to use the arch_cpu_is_hotpluggable() helper rather than arch_register_cpu(). Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> # On HiFive Unmatched Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/E1r5R4L-00Ct0d-To@rmk-PC.armlinux.org.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: liwei <liwei728@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
We want to make use of pte_next_pfn() outside of set_ptes(). Let's simply define PFN_PTE_SHIFT, required by pte_next_pfn(). Link: https://lkml.kernel.org/r/20240129124649.189745-6-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Mike Rapoport (IBM) <rppt@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Aneesh Kumar K.V <aneesh.kumar@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: David S. Miller <davem@davemloft.net> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Gerald Schaefer <gerald.schaefer@linux.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Naveen N. Rao <naveen.n.rao@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Russell King (Oracle) <linux@armlinux.org.uk> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit 57c254b) Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Normally, the hook is NOP. But for arches, such as RISC-V,
there are special livepatch symbols which do not need KLP
resolving. The RISC-V psABI said:
In the linker relaxation optimization, we introduce a concept
called relocation group; a relocation group consists of 1)
relocations associated with the same target symbol and can be
applied with the same relaxation, or 2) relocations with the
linkage relationship (e.g. `R_RISCV_PCREL_LO12_S` linked with
a `R_RISCV_PCREL_HI20`); all relocations in a single group must
be present in the same section, otherwise will split into another
relocation group.
When patches reference external non-exported globals, their
R_RISCV_PCREL_HI20/R_RISCV_PCREL_LO12_I relocations target the same
symbol and must live in the same section:
R_RISCV_PCREL_HI20 entry should be moved to .klp.rela.xxx section
when making patch, and when loading livepatch
core will resolve the target symbol address
R_RISCV_PCREL_LO12_I should also be moved to .klp.rela.xxx section
when making patch, but when loading livepatch
core MUST ignore it because R_RISCV_PCREL_LO12_I
indeed is just a link to the R_RISCV_PCREL_HI20
Signed-off-by: Kai Zhang <zhangkai@iscas.ac.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
It relies on openEuler livepatch-without-ftrace mechanism. Now only little-endian machine supported. Signed-off-by: Kai Zhang <zhangkai@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
ENTRY()/END()/WEAK() macros are deprecated and we should make use of the new SYM_*() macros [1] for better annotation of symbols. Replace the deprecated ones with the new ones and fix wrong usage of END()/ENDPROC() to correctly describe the symbols. [1] https://docs.kernel.org/core-api/asm-annotations.html Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231024132655.730417-3-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Yuntao Liu <liuyuntao12@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Patch series "Add update_mmu_tlb_range() to simplify code", v4. This series of commits mainly adds the update_mmu_tlb_range() to batch update tlb in an address range and implement update_mmu_tlb() using update_mmu_tlb_range(). After commit 19eaf44 ("mm: thp: support allocation of anonymous multi-size THP"), We may need to batch update tlb of a certain address range by calling update_mmu_tlb() in a loop. Using the update_mmu_tlb_range(), we can simplify the code and possibly reduce the execution of some unnecessary code in some architectures. This patch (of 3): Add update_mmu_tlb_range(), we can batch update tlb of an address range. Link: https://lkml.kernel.org/r/20240522061204.117421-1-libang.li@antgroup.com Link: https://lkml.kernel.org/r/20240522061204.117421-2-libang.li@antgroup.com Signed-off-by: Bang Li <libang.li@antgroup.com> Acked-by: David Hildenbrand <david@redhat.com> Cc: Chris Zankel <chris@zankel.net> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Lance Yang <ioworker0@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Let's make update_mmu_tlb() simply a generic wrapper around update_mmu_tlb_range(). Only the latter can now be overridden by the architecture. We can now remove __HAVE_ARCH_UPDATE_MMU_TLB as well. Link: https://lkml.kernel.org/r/20240522061204.117421-3-libang.li@antgroup.com Signed-off-by: Bang Li <libang.li@antgroup.com> Acked-by: David Hildenbrand <david@redhat.com> Cc: Chris Zankel <chris@zankel.net> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Lance Yang <ioworker0@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@5571c1e -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@1a8605c -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@4155b58 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@3f6658c -------------------------------- The standardized Zicbom extension supports only VA, however there's some vendor extensions (e.g. XtheadCmo) that can handle cache management operations on PA directly, bypassing the TLB lookup. Add a CMO alternatives macro variant that come with both VA and PA supplied, and the code can be patched to use either the VA or the PA at runtime. In this case the codepath is now patched to use VA for Zicbom and PA for XtheadCmo. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@398a132 -------------------------------- DMA synchorization is done on PA and the VA is calculated from the PA. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@1228510 -------------------------------- When doing DMA page preparation, both the VA and the PA are easily accessible from struct page. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@f28ac72 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@12094db -------------------------------- Originall the T-Head PBMT implementation in the kernel is intended for D1, thus the Sharable bit is not set. In addition, the Bufferable bit is not set for writecombine situation. Set these bits in the T-Head PBMT attributes definition. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@4ee05d6 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@3f4f975 -------------------------------- Author: xiaoguang.xing <xiaoguang.xing@sophgo.com> Date: Thu May 25 18:38:27 2023 +0800 Fix qspinlock issue that loops to call cpu_relax and not exit. The call trace is: queued_spin_lock_slowpath->arch_mcs_spin_lock_contended ->smp_cond_load_acquire. RISCV has not defined smp_cond_load_acquire, so it uses generic funtion that defined in include/asm-generic/barrier.h. The generic smp_cond_load_acquire calls smp_cond_load_relaxed that loops to call READ_ONCE and cpu_relax. The READ_ONCE need barrier after it to get the new value. Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@901e0a3 -------------------------------- Fix T-Head C9xx store merge buffer delay problem Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@25594db -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@e691c3f -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@2947481 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@20ea105 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@0f5ea06 -------------------------------- Sophgo SPI Flash Master Controller (SPIFMC) is a master controller to control serial SPI Flash. Enable CONFIG_SPI_SOPHGO_SPIFMC if you have a device with a SPIFMC controller and want to access the Flash as a mtd device. There is GD25LB512ME Serial Flash on SG2042 EVB, controlled by SPIFMC. Signed-off-by: jingyu.li01 <jingyu.li01@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@c12ed94 -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@0e7c830 -------------------------------- Signed-off-by: fengchun.li <fengchun.li@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@21778da -------------------------------- Turn on msi-x for top intr. Create msi-x whitelist, Limited the number of msi-x interrupts for inter x520 and wangxun NIC. Signed-off-by: chengjun.li <chengjun.li@sophgo.com> [Fixed conflicts with OLK-6.6] Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@f80bdad -------------------------------- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@a456dc0 -------------------------------- Signed-off-by: Icenowy Zheng <uwu@icenowy.me> [Fixed conflicts with Linux 6.6] Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
community inclusion category: feature bugzilla: https://gitee.com/openeuler/riscv-kernel/issues/I9DRVT Reference: xmzzz/linux-riscv@20cf5c8 -------------------------------- Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
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Kernel build success! |
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Lava check fail! result url: https://lava.oerv.ac.cn/scheduler/job/54 |
Collaborator
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开始测试 |
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Kernel build success! |
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Lava check fail! result url: https://lava.oerv.ac.cn/scheduler/job/55 |
Collaborator
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开始测试 |
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Kernel build success! |
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Lava check fail! result url: https://lava.oerv.ac.cn/scheduler/job/58 |
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/check |
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The config DRM_AMD_DC_DCN is absent in linux 6.6 branch, and AMDGPU
necessitates DRM_AMD_DC_FP.