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RISC-V Nacl扩展支持#260

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sterling-teng merged 18 commits into
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uestc-gr:nacl
Apr 30, 2026
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RISC-V Nacl扩展支持#260
sterling-teng merged 18 commits into
RVCK-Project:rvck-6.6from
uestc-gr:nacl

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@uestc-gr uestc-gr commented Apr 27, 2026 •
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issues: #256
所有补丁均来自L0社区

使用kvm unit test进行测试，测试通过
/home # ./lkvm-static run -k ./selftest.flat -m 64 -c 2 --name guest-200 --param
s "console=ttyS0"
Info: # lkvm run -k ./selftest.flat -m 64 -c 2 --name guest-200

##########################################################################

kvm-unit-tests

##########################################################################

PASS: selftest: program name
INFO: selftest: matched 7 command line parameters
SKIP: selftest: environ parsing
PASS: selftest: exceptions
INFO: selftest: CPU 0: hartid=00000000
INFO: selftest: CPU 1: hartid=00000001
PASS: selftest: Brought up all cpus
PASS: selftest: check_secondary
PASS: selftest: All secondaries are idle
SUMMARY: 7 tests, 0 unexpected failures, 1 skipped

clementleger and others added 18 commits April 23, 2026 16:04
@clementleger @uestc-gr
riscv: kvm: Use SYM_*() assembly macros instead of deprecated ones
1f1fb94 
mainline inclusion
from mainline-6.7-rc8
commit 683c5bb
category: feature
bugzilla: RVCK-Project#256

--------------------------------

ENTRY()/END()/WEAK() macros are deprecated and we should make use of the
new SYM_*() macros [1] for better annotation of symbols. Replace the
deprecated ones with the new ones and fix wrong usage of END()/ENDPROC()
to correctly describe the symbols.

[1] https://docs.kernel.org/core-api/asm-annotations.html

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@clementleger @uestc-gr
riscv: kvm: use ".L" local labels in assembly when applicable
0a91959 
mainline inclusion
from mainline-6.7-rc8
commit e5ff012
category: feature
bugzilla: RVCK-Project#256

--------------------------------

For the sake of coherency, use local labels in assembly when
applicable. This also avoid kprobes being confused when applying a
kprobe since the size of function is computed by checking where the
next visible symbol is located. This might end up in computing some
function size to be way shorter than expected and thus failing to apply
kprobes to the specified offset.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@ruanjinjie-eng @uestc-gr
riscv: stacktrace: Add USER_STACKTRACE support
c16f769 
mainline inclusion
from mainline-6.11
commit 1a74833
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Currently, userstacktrace is unsupported for riscv. So use the
perf_callchain_user() code as blueprint to implement the
arch_stack_walk_user() which add userstacktrace support on riscv.
Meanwhile, we can use arch_stack_walk_user() to simplify the implementation
of perf_callchain_user().

A ftrace test case is shown as below:

	# cd /sys/kernel/debug/tracing
	# echo 1 > options/userstacktrace
	# echo 1 > options/sym-userobj
	# echo 1 > events/sched/sched_process_fork/enable
	# cat trace
	......
	            bash-178     [000] ...1.    97.968395: sched_process_fork: comm=bash pid=178 child_comm=bash child_pid=231
	            bash-178     [000] ...1.    97.970075: <user stack trace>
	 => /lib/libc.so.6[+0xb5090]

Also a simple perf test is ok as below:

	# perf record -e cpu-clock --call-graph fp top
	# perf report --call-graph

	.....
	[[31m  66.54%[[m     0.00%  top      [kernel.kallsyms]            [k] ret_from_exception
            |
            ---ret_from_exception
               |
               |--[[31m58.97%[[m--do_trap_ecall_u
               |          |
               |          |--[[31m17.34%[[m--__riscv_sys_read
               |          |          ksys_read
               |          |          |
               |          |           --[[31m16.88%[[m--vfs_read
               |          |                     |
               |          |                     |--[[31m10.90%[[m--seq_read

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Tested-by: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/r/20240708032847.2998158-3-ruanjinjie@huawei.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@zcxGGmu @uestc-gr
riscv: perf: add guest vs host distinction
c067009 
mainline inclusion
from mainline-6.12-rc6
commit 5bb5ccb
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Introduce basic guest support in perf, enabling it to distinguish
between PMU interrupts in the host or guest, and collect
fundamental information.

Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/a67d527dc1b11493fe11f7f53584772fdd983744.1728957131.git.zhouquan@iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@zcxGGmu @uestc-gr
riscv: KVM: add basic support for host vs guest profiling
4b038f7 
mainline inclusion
from mainline-6.12-rc6
commit eded675
category: feature
bugzilla: RVCK-Project#256

--------------------------------

For the information collected on the host side, we need to
identify which data originates from the guest and record
these events separately, this can be achieved by having
KVM register perf callbacks.

Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/00342d535311eb0629b9ba4f1e457a48e2abee33.1728957131.git.zhouquan@iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Order the object files alphabetically
87e1168 
mainline inclusion
from mainline-6.12-rc6
commit e403a90
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Order the object files alphabetically in the Makefile so that
it is very predictable inserting new object files in the future.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-2-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Save/restore HSTATUS in C source
3e94b61 
mainline inclusion
from mainline-6.12-rc6
commit b6114a7
category: feature
bugzilla: RVCK-Project#256

--------------------------------

We will be optimizing HSTATUS CSR access via shared memory setup
using the SBI nested acceleration extension. To facilitate this,
we first move HSTATUS save/restore in kvm_riscv_vcpu_enter_exit().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-3-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Save/restore SCOUNTEREN in C source
3a9ddd4 
mainline inclusion
from mainline-6.12-rc6
commit b922307
category: feature
bugzilla: RVCK-Project#256

--------------------------------

The SCOUNTEREN CSR need not be saved/restored in the low-level
__kvm_riscv_switch_to() function hence move the SCOUNTEREN CSR
save/restore to the kvm_riscv_vcpu_swap_in_guest_state() and
kvm_riscv_vcpu_swap_in_host_state() functions in C sources.

Also, re-arrange the CSR save/restore and related GPR usage in
the low-level __kvm_riscv_switch_to() low-level function.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-4-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Break down the __kvm_riscv_switch_to() into macros
debfd6d 
mainline inclusion
from mainline-6.12-rc6
commit 8f57ada
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Break down the __kvm_riscv_switch_to() function into macros so that
these macros can be later re-used by SBI NACL extension based low-level
switch function.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-5-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Replace aia_set_hvictl() with aia_hvictl_value()
b80bb82 
mainline inclusion
from mainline-6.12-rc6
commit 5d8f7ee
category: feature
bugzilla: RVCK-Project#256

--------------------------------

The aia_set_hvictl() internally writes the HVICTL CSR which makes
it difficult to optimize the CSR write using SBI NACL extension for
kvm_riscv_vcpu_aia_update_hvip() function so replace aia_set_hvictl()
with new aia_hvictl_value() which only computes the HVICTL value.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-6-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Don't setup SGEI for zero guest external interrupts
a239519 
mainline inclusion
from mainline-6.12-rc6
commit 15ff2ff
category: feature
bugzilla: RVCK-Project#256

--------------------------------

No need to setup SGEI local interrupt when there are zero guest
external interrupts (i.e. zero HW IMSIC guest files).

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-7-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: Add defines for the SBI nested acceleration extension
65ec468 
mainline inclusion
from mainline-6.12-rc6
commit 5daf89e
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Add defines for the new SBI nested acceleration extension which was
ratified as part of the SBI v2.0 specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-8-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Add common nested acceleration support
ecbe4cd 
mainline inclusion
from mainline-6.12-rc6
commit d466c19
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Add a common nested acceleration support which will be shared by
all parts of KVM RISC-V. This nested acceleration support detects
and enables SBI NACL extension usage based on static keys which
ensures minimum impact on the non-nested scenario.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-9-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Use nacl_csr_xyz() for accessing H-extension CSRs
25c1de2 
mainline inclusion
from mainline-6.12-rc6
commit e28e6b6
category: feature
bugzilla: RVCK-Project#256

--------------------------------

When running under some other hypervisor, prefer nacl_csr_xyz()
for accessing H-extension CSRs in the run-loop. This makes CSR
access faster whenever SBI nested acceleration is available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-10-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Use nacl_csr_xyz() for accessing AIA CSRs
9a50d8d 
mainline inclusion
from mainline-6.12-rc6
commit dab5560
category: feature
bugzilla: RVCK-Project#256

--------------------------------

When running under some other hypervisor, prefer nacl_csr_xyz()
for accessing AIA CSRs in the run-loop. This makes CSR access
faster whenever SBI nested acceleration is available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-11-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Use SBI sync SRET call when available
35b26ff 
mainline inclusion
from mainline-6.12-rc6
commit 68c72a6
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Implement an optimized KVM world-switch using SBI sync SRET call
when SBI nested acceleration extension is available. This improves
KVM world-switch when KVM RISC-V is running as a Guest under some
other hypervisor.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-12-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit()
c967270 
mainline inclusion
from mainline-6.12-rc6
commit 3e7d154
category: feature
bugzilla: RVCK-Project#256

--------------------------------

Save trap CSRs in the kvm_riscv_vcpu_enter_exit() function instead of
the kvm_arch_vcpu_ioctl_run() function so that HTVAL and HTINST CSRs
are accessed in more optimized manner while running under some other
hypervisor.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-13-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@avpatel @uestc-gr
RISC-V: KVM: Use NACL HFENCEs for KVM request based HFENCEs
2cc613f 
mainline inclusion
from mainline-6.12-rc6
commit 5bdecd8
category: feature
bugzilla: RVCK-Project#256

--------------------------------

When running under some other hypervisor, use SBI NACL based HFENCEs
for TLB shoot-down via KVM requests. This makes HFENCEs faster whenever
SBI nested acceleration is available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-14-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
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github-actions Bot commented Apr 27, 2026 •
edited
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/24973693658

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/260/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA Template lava-job-template/qemu/qemu-ltp.yaml
Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

测试完成

详细结果:

RVCK result

check result
kunit-test success
kernel-build success
lava-trigger success
check-patch success

Kunit Test Result

[02:33:00] Testing complete. Ran 457 tests: passed: 445, skipped: 12

Kernel Build Result

Kernel build succeeded: RVCK-Project/rvck/260_24973693658_1/

6c3ac597324c2ae531d12a3e498a18da /srv/guix_result/2cc613f07b26d1ed002fb075329b0184cbab7f60/Image
d2c935cb9d295b28a5f819f797f1a8a4 /root/initramfs.img

LAVA Check

args value
testcase_repo RVCK-Project/lavaci
testcase_ref main
lava_template lava-job-template/qemu/qemu-ltp.yaml
testcase_path lava-testcases/common-test/ltp/ltp.yaml
testitem_name RVCK-Project_rvck_pull_request_target_260__common-test_qemu
kernel_download_url https://repo.tarsier-infra.isrc.ac.cn/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/260_24973693658_1/Image
initramfs_download_url https://repo.tarsier-infra.isrc.ac.cn/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/260_24973693658_1/initramfs.img
rootfs_download_url https://fast-mirror.isrc.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/RVCK/openEuler24.03-LTS-SP1/openeuler-rootfs.img.zst

result: Lava check done!

Check Patch Result
Total Errors 0
Total Warnings 19

@uestc-gr
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uestc-gr commented Apr 28, 2026

PR已经完成并通过自测，所有的补丁来源于L0社区，请老师评审

@sterling-teng
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sterling-teng commented Apr 28, 2026

PR已经完成并通过自测，所有的补丁来源于L0社区，请老师评审

好的。

@sterling-teng
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sterling-teng commented Apr 29, 2026

该pr还未进行物理机测试，rebase窗口只剩下一天了，明天我如果能测试完，就尝试合并。

@sterling-teng sterling-teng merged commit 35ccb1d into RVCK-Project:rvck-6.6 Apr 30, 2026
50 checks passed
@uestc-gr uestc-gr deleted the nacl branch May 7, 2026 01:49
@ieiao ieiao mentioned this pull request May 14, 2026
Merged
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6 participants

@uestc-gr @sterling-teng @clementleger @ruanjinjie-eng @zcxGGmu @avpatel