Add SQ8↔FP16 ARM SIMD distance kernels [MOD-14972]

[dor-forer]

Describe the changes in the pull request

Add asymmetric SQ8↔FP16 SIMD distance kernels (IP, L2, Cosine) for ARM tiers: NEON_HP, SVE, SVE2. Stacked on PR #970 (MOD-14954), which delivers the x86 equivalents.

The SVE hot loop uses svld1uh_u32 to zero-extend each FP16 halfword into a 32-bit lane, allowing svcvt_f32_f16_x to read the correct bits directly. The NEON residual mirrors the SQ8_FP32 NEON sister: three independent 4-lane sub-steps (r>=4/8/12) leaving at most 3 elements for scalar, replacing the previous single 8-lane block + up-to-7 software conversions.

Which issues this PR fixes

1. MOD-14972

Main objects this PR modified

1. src/VecSim/spaces/IP/IP_NEON_SQ8_FP16.h — new NEON_HP IP kernel
2. src/VecSim/spaces/IP/IP_SVE_SQ8_FP16.h — new SVE/SVE2 IP kernel
3. src/VecSim/spaces/L2/L2_NEON_SQ8_FP16.h — new NEON_HP L2 kernel
4. src/VecSim/spaces/L2/L2_SVE_SQ8_FP16.h — new SVE/SVE2 L2 kernel
5. src/VecSim/spaces/functions/NEON_HP.{h,cpp}, SVE.{h,cpp}, SVE2.{h,cpp} — chooser symbols
6. src/VecSim/spaces/IP_space.cpp, L2_space.cpp — AArch64 dispatcher blocks
7. tests/unit/test_spaces.cpp — tier-walk tests for NEON_HP / SVE / SVE2
8. tests/benchmark/spaces_benchmarks/bm_spaces_sq8_fp16.cpp — ARM microbench registrations

Mark if applicable

• This PR introduces API changes
• This PR introduces serialization changes

---

Note

Medium Risk
Changes hot-path vector distance math and CPU dispatch; incorrect SIMD or residual handling could skew ANN results, though extensive parity tests mitigate this.

Overview
Adds ARM SIMD for asymmetric SQ8 storage ↔ FP16 query distances (inner product, L2, cosine), paralleling the existing x86 SQ8↔FP16 path.

New NEON_HP kernels use 16-byte chunks, FP16→FP32 widening, and a residual path aligned with the SQ8↔FP32 NEON style. New SVE/SVE2 IP kernels load FP16 via svld1uh_u32 and widen with svcvt_f32_f16; L2 reuses the IP core plus sum-of-squares metadata.

Dispatch in IP_space.cpp and L2_space.cpp selects SVE2 → SVE → NEON_HP when dim >= 16 and the matching CPU features are present. Chooser wiring lives in NEON_HP, SVE, and SVE2 function modules.

Tests/benchmarks: unit tests walk each ARM tier and compare to baseline; GetDistFuncSQ8FP16Asymmetric uses dim=15 for portable scalar checks; benchmarks register NEON_HP, SVE, and SVE2 variants.

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[jit-ci]

🛡️ Jit Security Scan Results

✅ No security findings were detected in this PR

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^{Security scan by Jit}

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 97.07%. Comparing base (999580f) to head (6f6ef26).
⚠️ Report is 1 commits behind head on dor-forer-sq8-fp16-x86-kernels-mod-14954.

Additional details and impacted files

@@                             Coverage Diff                              @@
##           dor-forer-sq8-fp16-x86-kernels-mod-14954     #973      +/-   ##
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+ Coverage                                     97.04%   97.07%   +0.03%     
============================================================================
  Files                                           141      141              
  Lines                                          8110     8110              
============================================================================
+ Hits                                           7870     7873       +3     
+ Misses                                          240      237       -3     

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