v0.1.13

Full Changelog: v0.1.12...v0.1.13

v0.1.12

Full Changelog: v0.1.11...v0.1.12

Factory flashing (STM32F103C8)

• pmic_stm32f103_v0.1.12-20261110.hex merges the bootloader and application for the current STM32F103C8 target (0x08000000-0x0800B383). It is also inside stm32f103c8_firmware.tar.gz.
• Flash with STM32CubeProgrammer or J-Flash, then verify FW_VER:0.1.10;.
• GD32F503 firmware is withheld because GD32_HARDWARE_VERIFIED is not true.
• SHA256: b62b816b84b1e18dfeaf50984723ac4de774dbf4133a3dba03a0433a4e37578a

v0.1.11 engineering prerelease

Engineering prerelease: STM32F103C8 serial OTA and GD32F503VET6 reference build.

• Exactly two target archives: stm32f103c8_firmware.tar.gz and gd32f503_firmware.tar.gz. Each contains bootloader and application images plus SHA256SUMS.
• STM32 application reports FW_VER:0.1.10; without the historical -left suffix. The resident USART3 bootloader supports direct 64-byte-block updates, CRC32 verification, and recovery by retransmitting after an interrupted update. The first bootloader installation still requires SWD. There is no second image slot or automatic rollback.
• The tagged STM32 application was transferred via the A100 serial tunnel to the STM32F103C8 board (UID 0669FF555553787287104058). The 41,860-byte SWD readback matched the release image SHA-256 97610bcb09917f8fa8fd6ad1dd2e3b759549ebeb3f3f27ed28a86b685bf989be. Read-only serial HIL passed 6/6 at 1.5 V input, CHG_EN=0, no battery attached. Earlier tests verified an interrupted update remained in the bootloader and could be retransmitted.
• GD32F503VET6 bootloader and application compile and link, but there is no matching verified board. Its reference pinout is software-defined and charging EN remains disabled. GD32 flash, OTA, and loaded charging have not been tested on hardware.

These are engineering candidates, not production-qualified charging firmware. Flashing remains an operator action.

Factory flashing (STM32F103C8)

• PMIC_all.hex is the merged bootloader + application image for the current STM32F103C8 target. It covers 0x08000000-0x0800B383.
• Flash it once with STM32CubeProgrammer (Full chip erase, then Open file -> PMIC_all.hex -> Start Programming, Verify on) or J-Flash (Program & Verify).
• The original two-file flow (boot.hex at 0x08000000 + ChargeBAT.hex at 0x08001000) remains valid.
• SHA256: 76d0229c32a9c3d2ed99f97c67fe88dffa8d1de8d39308cb62e87824c635d069

v0.1.10 engineering candidate

Engineering prerelease. Two application targets, not production-qualified.

• STM32F103C8 app FW_VER 0.1.9-left; GD32F503VET6 app FW_VER 0.1.1-gd32.
• CHRG_INFO now includes CHG_FAULT:0/1 before CHG_EN. It reports the MCU's latched exception bit without changing charge control.
• STM32F103C8 0.1.9-left was flashed on 2026-11-06 at 0x08001000 with Horco CMSIS-DAP 3181740232 and read back byte for byte. Read-only serial HIL passed 6/6 at both 5 V (CHG_FAULT=0, CHG_EN=0) and 20 V PD (CHG_FAULT=0, CHG_EN=1), with no battery connected. A valid-format OTA_BEGIN request returned OTA_ERR; SWD readback afterward confirmed the application was unchanged. A loaded charging test was not performed.
• GD32 uses a software-defined pinout with no matching verified board; its default build keeps charging EN disabled. GD32 flashing and OTA remain untested.
• Flashing remains a manual operator action. Do not use the GD32 archive as a production image.

PMIC v0.1.9 engineering prerelease

PMIC v0.1.9 engineering prerelease

This release replaces v0.1.8, whose GD32 asset reported the wrong FW_VER. Two firmware bundles are attached, each with boot.bin/hex, application bin/hex, and SHA256SUMS. They were built by CI run 42032683457 from commit c846bbc; both image hashes and embedded version strings were checked.

STM32F103C8: FW_VER 0.1.8-left. PA4 is charge red, PA5 charge green, PA6 battery green, and PA7 battery red. The 0.1.8-left control logic was tested on an STM32 board at 5 V and 20 V with no battery connected, and its application was flashed and read back. The CI rebuild embeds its own build-time string. Use SWD at boot 0x08000000 and app 0x08001000; serial OTA is unsupported.

GD32F503VET6 reference target: FW_VER 0.1.0-gd32. The RT-Thread bootloader and application include UART identity/status, ADC, GPIO, PWM, CH224/TMP100 I2C, and internal-Flash OTA. The pinout is software-defined without a verified matching board. The default CI application forces charging EN off. GD32 runtime, OTA, and electrical behavior have not been tested on hardware. Do not use this image to charge a battery or flash an unverified board.

Neither image is production-qualified. Loaded charging, measurement calibration, charge cutoff, GD32 pinout, and OTA power-loss behavior require board-level testing. The 54 V threshold changes the STM32 indicator only; independent battery cutoff protection is required.

PMIC v0.1.8 SUPERSEDED

SUPERSEDED: Do not use the GD32 asset from this release. Its FW_VER reports the STM32 string 0.1.8-left because of a build-condition error. Use the corrected release once available.

PMIC v0.1.8 engineering prerelease

Exactly two firmware bundles are attached: stm32f103c8_firmware.tar.gz and gd32f503_firmware.tar.gz. Each contains boot.bin/hex, application bin/hex, and SHA256SUMS. Both bundles come from successful CI run 42027546124 at commit 03834dc.

STM32F103C8: FW_VER 0.1.8-left. PA4 is charge red, PA5 charge green, PA6 battery green, and PA7 battery red. The 0.1.8-left application was flashed, read back, and checked at 5 V and 20 V with no battery connected. The release rebuild embeds a different RT-Thread build-time string; charging logic is unchanged. Use SWD at boot 0x08000000 and app 0x08001000. Serial OTA is unsupported.

GD32F503VET6 reference target: FW_VER 0.1.0-gd32. Boot/app/staging/config occupy the first 512 KB of Flash; SRAM is 64 KB. The linked RT-Thread application includes UART identity/status commands, ADC, GPIO, PWM, CH224/TMP100 I2C and internal-Flash OTA. The pinout is software-defined and has no matching verified board. The default CI image forces charging disabled regardless of measured inputs. Do not use it to charge a battery or flash an unverified board. GD32 OTA and runtime behavior have only compile and image-structure evidence, not hardware validation.

Neither image is production-qualified. Loaded charging, current/voltage calibration, charge cutoff, GD32 pinout, and OTA power-loss behavior need board-level validation. The 54 V threshold changes the STM32 lamp, not charge termination; a battery pack with independent cutoff protection is required.

v0.1.7

STM32F103 PMIC firmware v0.1.7 (engineering candidate)

SUPERSEDED: Do not flash this release for charge-indicator use. Hardware GPIO testing on 2026-11-05 confirmed PA4 drives the red charge LED and PA5 drives the green charge LED. This v0.1.7 image has those colors reversed. The corrected v0.1.8-left application has been flashed and read back on the STM32F103C8 test board; use a newer release once published.

• Left layout: FW_VER 0.1.7-left. PA4 drives the green charge LED while charging below 54 V battery/output voltage. PA5 drives the red LED while charging at or above 54 V. Both are off when charging is disabled.
• PA6 is high when the PA1 ADC pin reads 1.39-1.50 V, inclusive. PA7 is high at 1.21-<1.39 V. At 1.39 V, PA6 takes priority. Both are off outside these ranges or after an ADC sampling failure.
• Left-layout host R/G writes no longer override the automatic status LEDs. Right-layout firmware behavior and FW_VER 0.1.2-right remain unchanged.
• Select the matching board archive. Bootloader address: 0x08000000. Application address: 0x08001000. The left layout does not support serial OTA; use SWD.

Validation: host boundary tests, command guard, HIL protocol self-test, and left/right cross-builds passed. CI built this tag. v0.1.7-left has not been flashed or tested on the board. The earlier v0.1.5-left control logic was tested at 5 V and 20 V with no battery pack connected.

This is not production-qualified charging firmware. The 54 V threshold changes only the lamp, not the charge control or termination. A battery pack with independent charge cutoff protection is required. External LED voltages, loaded charge current, temperature, ADC calibration, and charge termination remain unverified.

v0.1.6

STM32F103 PMIC firmware v0.1.6 (engineering candidate)

• Left layout: FW_VER 0.1.6-left. Automatically enables PB3 EN and PA3 ICTRL after three valid ADC samples when the input is 16-32 V, CH224 reports available current, and no fault is latched. BMS/USART1 and PB4 are unused.
• Right layout: FW_VER 0.1.2-right; application behavior is unchanged. The CI binary has a new embedded RT-Thread build timestamp.
• Each layout archive contains boot.bin, boot.hex, ChargeBAT.bin, ChargeBAT.hex, and SHA256SUMS. Bootloader address: 0x08000000. Application address: 0x08001000. Select the matching board layout.

Validation: v0.1.6 built in CI. The same left-layout control logic in v0.1.5-left was flashed and tested on one STM32F103C8 board: 5 V Type-C kept EN low; 20 V PD set PB3 high and TIM2 CCR4 to 5040. The test had no battery pack connected. v0.1.6-left itself has not been flashed.

Not qualified for production charging. A battery pack with independent charge cutoff protection is required. Loaded charge current, charge termination, external EN voltage, temperature, and ADC calibration remain unverified.