FIFO Module

Overview

This project contains a Verilog-based implementation of a Synchronous FIFO (First-In, First-Out) memory. A FIFO operates in a first-in, first-out manner, meaning the data written into the memory first will be read out first. This particular FIFO design is synchronous, meaning both the write and read operations are synchronized to a single clock signal (clk), making it suitable for designs where the read and write operations are driven by the same clock domain.

Features:

1. Data Width: 8-bit wide data bus (parameterized).
   
2. Depth: Default FIFO depth is 16 (parameterizable).
   
3. Status Signals:
      empty: Indicates whether the FIFO is empty (i.e., no data available to read).
      full: Indicates whether the FIFO is full (i.e., no more space available to write).
   
4. Reset Signal: The FIFO can be reset asynchronously, setting the read and write pointers to zero and marking the FIFO as empty.
   
5. Parameterizable Pointers: FIFO uses parameterized write (wr_ptr) and read (rd_ptr) pointers for flexibility in different depth configurations.
   
6. Write/Read Enable: Independent write_en and read_en signals control whether the module writes or reads from the memory.
   

Synchronous FIFO:

This design is a synchronous FIFO, meaning that both read and write operations occur on the rising edge of the clock (clk). The read and write pointers (wr_ptr and rd_ptr) update in sync with the clock, ensuring that data movement through the FIFO is predictable and consistent.

Signals

Input Signals:

1. clk: The system clock, driving both read and write operations synchronously.
   
2. reset: Asynchronous reset signal, used to reset the FIFO to an initial state.
   
3. write_en: Enables writing of data into the FIFO when asserted.
   
4. read_en: Enables reading of data from the FIFO when asserted.
   
5. data_in [7:0]: 8-bit input data to be written into the FIFO.
   

Output Signals:

1. data_out [7:0]: 8-bit output data from the FIFO. It outputs the next available data only if the FIFO is not empty.
   
2. empty: A status signal indicating when the FIFO is empty.
   
3. full: A status signal indicating when the FIFO is full.
   

Internal Logic

Write Operation:

Data is written into the FIFO at the location pointed to by wr_ptr (write pointer).
After each write operation, wr_ptr is incremented by 1.
The FIFO becomes full when the wr_ptr advances to the position directly before the rd_ptr (read pointer).

Read Operation:

Data is read from the FIFO at the location pointed to by rd_ptr.
After each read operation, rd_ptr is incremented by 1.
The FIFO becomes empty when the rd_ptr catches up to the wr_ptr.

Empty and Full Status:

The empty signal is asserted when wr_ptr and rd_ptr are equal, indicating no data is available for reading.
The full signal is asserted when the write pointer is one position behind the read pointer, meaning the FIFO has no available space for writing new data.

Parameterization:

The FIFO is designed to be configurable with the following parameters:

1. DEPTH: Defines the depth (number of entries) in the FIFO memory. The default value is 16.
   
2. DATA_WIDTH: Defines the width of each data word. The default value is 8 bits.
   
3. PTR_SIZE: Defines the size of the write and read pointers, which is determined by the depth of the FIFO.
   

This synchronous FIFO module is a flexible and robust design for buffering data in FPGA projects. It can be used in applications where data needs to be written and read at different times but synchronized to the same clock signal. With adjustable depth and data width parameters, the FIFO can be tailored to meet various data buffering needs.