RISC-Vproject

This is my project work on "Synergising RISC-V Core with Low Power FIR Filtering on FPGA for Enhanced Processing Efficiency"

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
Pipeline_Stage3.v		Pipeline_Stage3.v
README.md		README.md
imm_gen.v		imm_gen.v
immediate_generation.v		immediate_generation.v
ms_riscv32_mp.v		ms_riscv32_mp.v
msrv32_instruction_mux.v		msrv32_instruction_mux.v
msrv32_integer_file.v		msrv32_integer_file.v
msrv32_pc.v		msrv32_pc.v
msrv32_wr_en_generator.v		msrv32_wr_en_generator.v
pipeline_stage_1.v		pipeline_stage_1.v

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