Skip to content
View Sashidhar077's full-sized avatar

Block or report Sashidhar077

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Automated_RTL_Regression_Framework Automated_RTL_Regression_Framework Public

    Verilog 1

  2. project_calculator project_calculator Public

    Verilog

  3. UART_Transmitter_and_Receiver-Verilog-FSM UART_Transmitter_and_Receiver-Verilog-FSM Public

    Verilog

  4. RISC-V_5_Stage_Pipelined_Processor_RV32I RISC-V_5_Stage_Pipelined_Processor_RV32I Public

    Verilog

  5. AXI4_Lite_LED_Controller AXI4_Lite_LED_Controller Public

    Verilog