SiliconLanguage
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- monadic-hypervisor Public
A bare-metal, zero-kernel Type-1 hypervisor for the device-edge-cloud continuum. Written in Rust for ARM64 (EL2) and RISC-V, it enables true PCIe bypass and hardware-hardened OS services to eliminate kernel tax for AI and IoT workloads. Rust’s strict ownership model and strong typing enforce safety at compile time through zero-cost abstractions.
SiliconLanguage/monadic-hypervisor’s past year of commit activity - dataplane-emu Public
A hardware-accurate C++ data plane emulator for high-performance storage and networks. Simulates lock-free SPDK/io_uring queues, DPDK-style thread-per-core execution, and NVMe-oF architectures
SiliconLanguage/dataplane-emu’s past year of commit activity - mempool Public Forked from pulp-platform/mempool
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
SiliconLanguage/mempool’s past year of commit activity - SiliconLanguage.github.io Public
The official engineering diary of SiliconLanguage. Documenting deep-tech explorations in hardware-software co-design, kernel-bypass networks (SPDK/io_uring), Agentic AI orchestration, and bare-metal ARM64/RISC-V optimizations.
SiliconLanguage/SiliconLanguage.github.io’s past year of commit activity - tensorplane Public
An enterprise-grade AI data plane accelerator achieving true zero-copy I/O. Inspired by DeepSeek 3FS USRBIO, it separates command and data queues for GPUDirect RDMA streaming and SmartNIC/DPU offloading, bypassing POSIX bottlenecks for hyperscale AI workloads.
SiliconLanguage/tensorplane’s past year of commit activity
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