v0.3.0: 2024 ICRC Submission Edition v1

What's Changed

• Support for fire_like_ravens parameter by @keegandent in #25
• Change to Verilog implementation of AXI4-Stream interface by @keegandent in #29
• DBSCAN network and input spikes example courtesy of @jimplank
• UART Buffer Size Accommodation and Speed Improvement by @keegandent in #36
• Demo Related Fixes and Performance Improvements by @keegandent in #37, with help from @BGull00, @charizzo, @jimplank
• Hotfix for #38 by @keegandent in #39, reported by @BGull00
• Relative instead of absolute timestamps for apply_spike* and output_* by @keegandent in #41, reported by @BGull00 in #40
• Support for Intel Altera FPGAs and Cyclone V GX board by @keegandent in #42

To Readers of the 2024 ICRC Paper Submission

Please note that versions after v0.3.0, particularly v0.4 or later, may behave quite differently than described in the paper, as we have already discovered areas we can make improvements. We appreciate you understanding the dynamic nature of this research and development.

Full Changelog: v0.2.1...v0.3.0