Bug: Combinational SC-CLR triggers premature Sequence Counter reset, skipping states (Fixed using bandage)

[TabishShahMohsin]

Description:

• An issue has been identified in the Control Unit timing logic where the Sequence Counter (SC) resets to T0 prematurely. When the combinational logic for SC-CLR evaluates to True during state Ti, the reset somehow occurs on the same clock edge. This causes the system to skip state Ti entirely and jump straight back to T0, preventing any control functions mapped to Ti from executing.

Current Workaround:

• Right now I have literally changed the combinational circuit of the SC, such whenever it needed $T_i$, it simply takes in $T_{i+1}$
• While this allows $T_i$ to execute properly before the reset takes effect, it functions as a hardcoded delay rather than a clean architectural solution.

[TabishShahMohsin]

3ea41c7