[feature] arm: speed up fp16 exp_ps floor step on aarch64

[crafcat7]

This PR is an improvement upon #6657, supplementing and optimizing exp_ps for ARM fp16 scenarios, maintaining consistency with the ARM fp32 implementation.

The performance improvement is due to reduced SIMD instruction computation and the replacement of the original generic floor processing with native instructions:

Optimization: Use vcvtmq_s16_f16 for floor on aarch64

• Legacy: 6 instructions (vcvt + vcvt + vclt + vand + vsub + vcvt)
• New: 2 instructions (vcvtmq + vcvt) + reuse for 2^n

Performance and accuracy are as follows (tested on Android devices), and it is expected to improve speed by 20-30%.

elements=1048576 rounds=10000

--- pack4 (4 x fp16 elements) ---
legacy exp_ps_f16 : 1.959 ns/elem
new exp_ps_f16 : 1.486 ns/elem
speedup : 1.32x

--- pack8 (8 x fp16 elements) ---
legacy exp_ps_f16 : 1.203 ns/elem
new exp_ps_f16 : 0.864 ns/elem
speedup : 1.39x

--- Accuracy ---
legacy vs new avg diff : 0.000000000
legacy vs new max diff : 0.000000000

Testing method: Execute fn in batches using SIMD and measure the throughput performance per element.

static float bench_fn_pack4(const std::vector<float>& data, int rounds, float16x4_t (*fn)(float16x4_t))
{
    volatile float sink = 0.f;
    const auto t0 = std::chrono::steady_clock::now();

    for (int r = 0; r < rounds; r++)
    {
        float16x4_t vacc = vdup_n_f16(0.f);
        for (size_t i = 0; i + 3 < data.size(); i += 4)
        {
            // Convert float to fp16
            float32x4_t x_f32 = vld1q_f32(&data[i]);
            float16x4_t x = vcvt_f16_f32(x_f32);
            vacc = vadd_f16(vacc, fn(x));
        }
        sink += hsum4_f16(vacc);
    }

    const auto t1 = std::chrono::steady_clock::now();
    const std::chrono::duration<double, std::nano> dt = t1 - t0;
    if (sink == 0.123f)
        std::printf("ignore %f\n", sink);
    return (float)(dt.count() / (double)(data.size() * (size_t)rounds));
}

static float bench_fn_pack8(const std::vector<float>& data, int rounds, float16x8_t (*fn)(float16x8_t))
{
    volatile float sink = 0.f;
    const auto t0 = std::chrono::steady_clock::now();

    for (int r = 0; r < rounds; r++)
    {
        float16x8_t vacc = vdupq_n_f16(0.f);
        for (size_t i = 0; i + 7 < data.size(); i += 8)
        {
            float32x4_t x_f32_0 = vld1q_f32(&data[i]);
            float32x4_t x_f32_1 = vld1q_f32(&data[i + 4]);
            float16x4_t x0 = vcvt_f16_f32(x_f32_0);
            float16x4_t x1 = vcvt_f16_f32(x_f32_1);
            float16x8_t x = vcombine_f16(x0, x1);
            vacc = vaddq_f16(vacc, fn(x));
        }
        sink += hsum8_f16(vacc);
    }

    const auto t1 = std::chrono::steady_clock::now();
    const std::chrono::duration<double, std::nano> dt = t1 - t0;
    if (sink == 0.123f)
        std::printf("ignore %f\n", sink);
    return (float)(dt.count() / (double)(data.size() * (size_t)rounds));
}

[nihui]

#if defined(__aarch64__) is always true for all armv8.2+ targets
the macro condition is unnecessary

[crafcat7]

#if defined(__aarch64__) is always true for all armv8.2+ targets the macro condition is unnecessary

Get. I removed the check for aarch64. Optimizations are always used in ARM fp16 implementations.

[codecov-commenter]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 93.79%. Comparing base (16beb34) to head (c38d865).

Additional details and impacted files

@@            Coverage Diff             @@
##           master    #6659      +/-   ##
==========================================
- Coverage   93.80%   93.79%   -0.01%     
==========================================
  Files         917      917              
  Lines      288669   288475     -194     
==========================================
- Hits       270776   270581     -195     
- Misses      17893    17894       +1     

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[nihui]

I suspect that vrndmq_f16 and vcvtq_s16_f16 would be better, because this would delay a register allocation and reduce one register dependency, similar to how FP32 does it.

[crafcat7]

I suspect that vrndmq_f16 and vcvtq_s16_f16 would be better, because this would delay a register allocation and reduce one register dependency, similar to how FP32 does it.

Yes, I tried using vrndmq_f16 + vcvtq_s16_f16 and it is indeed faster than the vcvtm.

elements=1048576 rounds=10000

--- pack4 (4 x fp16 elements) ---
legacy exp_ps_f16 : 1.962 ns/elem
vcvtm  exp_ps_f16 : 1.482 ns/elem
rnd    exp_ps_f16 : 1.467 ns/elem

legacy/vcvtm      : 1.32x
rnd/vcvtm         : 0.990x

--- pack8 (8 x fp16 elements) ---
legacy exp_ps_f16 : 1.203 ns/elem
vcvtm  exp_ps_f16 : 0.861 ns/elem
rnd    exp_ps_f16 : 0.858 ns/elem

legacy/vcvtm  : 1.40x
rnd/vcvtm     : 0.997x

--- Accuracy ---
legacy vs new avg diff  : 0.000000000
legacy vs new max diff  : 0.000000000
new vs rnd   avg diff   : 0.000000000
new vs rnd   max diff   : 0.000000000

Therefore, I submitted another change, using vrndmq_f16 + vcvtq_s16_f16 to reduce register dependencies.

[nihui]

Thanks for your contribution !