This project has no active crowdfunding, donation, or fundraising campaigns of any kind.
If you have encountered any solicitation for donations related to GargantuRAM or the 5500FP processor — including on VK, Telegram, or any other platform — it is not authorized by the author and has no affiliation with this project.
The sole author and maintainer of the Ternary Computer System initiative is Claudio La Rosa, based in Italy.
Official channels: ternary-computing.com | Zenodo paper
The GargantuRAM 1.5 PRE is the reference development board for the 5500FP CPU module. It accepts the CPU module via an edge connector and provides all the supporting infrastructure needed to run and program the processor: static RAM, mass storage, serial communication, and a ternary/binary bridge that adapts the signals of the 5500FP ternary CPU to the binary circuitry of this board, allowing immediate use of standard binary peripherals.
The board is implemented on an Efinix Trion T120F484 FPGA and clocked at 20 MHz via a dedicated on-board oscillator, ensuring a clean and stable reference for the CPU module.
| Interface | Details |
|---|---|
| CPU Module connector | Edge connector for the 5500FP CPU module |
| Static RAM | Three ISS static RAM modules (RAM_0, RAM_1, RAM_2) |
| SPI ROM | Non-volatile storage for boot code and firmware images |
| SPI SD card | Removable mass storage for programs and data |
| Serial interfaces | 2× UART over USB (SER_1USB, SER_2) — program loading and host communication |
| Power section | On-board power regulation |
Altium Project/— Project files for Altium.Img/— Photo and rendering.Docs/— Schematics and documentations.
Note on PCB routing: The current layout is fully functional and has been used to produce verified physical boards (MiniITX form factor). The routing is not yet optimized — improvements are planned for a future revision. Contributions and review from experienced PCB designers are welcome.
| Repository | Contents |
|---|---|
| GargantuRAM_ROM | Firmware for the SPI ROM |
| GargantuRAM_VHDL | FPGA source code (VHDL) |
This project is released under the CERN-OHL-P v2 license.
See the LICENSE file for the full text.
Any Product made using this Source must include the following notice:
"This Product is based on CERN‑OHL‑P licensed Source, available at https://github.com/Ternary-Computer-System/GargantuRAM."
For more details about the Ternary Computer System:
https://www.ternary-computing.com
