Test setup for vhdl_testbench

inverter/__init__.py

@@ -153,7 +153,7 @@ def run(self,*arg):
                 """
             else:
                 interactive_control_contents="""
-                    add wave -position insertpoint \\
+                    add wave \\
                     sim/:tb_inverter:A \\
                     sim/:tb_inverter:initdone \\
                     sim/:tb_inverter:clock \\
@@ -166,17 +166,24 @@ def run(self,*arg):
                 _=rtl_iofile(self, name='A', dir='in', iotype='sample', ionames=['A'], datatype='sint') # IO file for input A
                 f=rtl_iofile(self, name='Z', dir='out', iotype='sample', ionames=['Z'], datatype='sint')
                 # This is to avoid sampling time confusion with Icarus
-                f.verilog_io_sync='@(negedge clock)'
-                self.rtlparameters=dict([ ('g_Rs',self.Rs),]) # Defines the sample rate
+                if self.lang == 'sv':
+                    f.rtl_io_sync='@(negedge clock)'
+                elif self.lang == 'vhdl':
+                    f.rtl_io_sync='falling_edge(clock)'
+
+                self.rtlparameters=dict([ ('g_Rs',('real',self.Rs)),]) # Defines the sample rate
                 self.interactive_control_contents=interactive_control_contents
                 self.run_rtl()
                 self.IOS.Members['Z'].Data=self.IOS.Members['Z'].Data[:,0].astype(int).reshape(-1,1)
             elif self.model=='vhdl':
                 # VHDL simulation options here
                 _=rtl_iofile(self, name='A', dir='in', iotype='sample', ionames=['A']) # IO file for input A
                 f=rtl_iofile(self, name='Z', dir='out', iotype='sample', ionames=['Z'], datatype='int')
-                f.verilog_io_sync='@(negedge clock)'
-                self.rtlparameters=dict([ ('g_Rs',self.Rs),]) # Defines the sample rate
+                if self.lang == 'sv':
+                    f.rtl_io_sync='@(negedge clock)'
+                elif self.lang == 'vhdl':
+                    f.rtl_io_sync='falling_edge(clock)'
+                self.rtlparameters=dict([ ('g_Rs',('real',self.Rs)),]) # Defines the sample rate
                 self.interactive_control_contents=interactive_control_contents
                 self.run_rtl()
                 self.IOS.Members['Z'].Data=self.IOS.Members['Z'].Data.astype(int).reshape(-1,1)
@@ -263,11 +270,17 @@ def define_io_conditions(self):
         '''This overloads the method called by run_rtl method. It defines the read/write conditions for the files
 
         '''
-        # Input A is read to verilog simulation after 'initdone' is set to 1 by controller
-        self.iofile_bundle.Members['A'].verilog_io_condition='initdone'
-        # Output is read to verilog simulation when all of the outputs are valid, 
-        # and after 'initdone' is set to 1 by controller
-        self.iofile_bundle.Members['Z'].verilog_io_condition_append(cond='&& initdone')
+        if self.lang == 'sv':
+            # Input A is read to verilog simulation after 'initdone' is set to 1 by controller
+            self.iofile_bundle.Members['A'].rtl_io_condition='initdone'
+            # Output is read to verilog simulation when all of the outputs are valid, 
+            # and after 'initdone' is set to 1 by controller
+            self.iofile_bundle.Members['Z'].rtl_io_condition_append(cond='&& initdone')
+        elif self.lang == 'vhdl':
+            self.iofile_bundle.Members['A'].rtl_io_condition='(initdone = \'1\')'
+            # Output is read to verilog simulation when all of the outputs are valid, 
+            # and after 'initdone' is set to 1 by controller
+            self.iofile_bundle.Members['Z'].rtl_io_condition_append(cond='and initdone = \'1\'')
 
 if __name__=="__main__":
     import argparse
@@ -286,14 +299,18 @@ def define_io_conditions(self):
 
     length=2**8
     rs=100e6
-    controller=inverter_controller()
+    #Testbench vhdl
+    #lang='vhdl'
+    lang='vhdl'
+    controller=inverter_controller(lang=lang)
     controller.Rs=rs
     #controller.reset()
     #controller.step_time()
     controller.start_datafeed()
-
     #By default, we set only open souce simulators
-    models=['py', 'icarus', 'ngspice' ]
+    #dut is verilog 
+    models=['sv']
+    #models=['icarus']
     #models=['py','sv' 'icarus','vhdl','eldo','spectre']
     # Here we instantiate the signal source
     duts=[]
@@ -305,8 +322,9 @@ def define_io_conditions(self):
         d=inverter()
         duts.append(d) 
         d.model=model
+        d.lang=lang
         d.Rs=rs
-        #d.preserve_rtlfiles = True
+        d.preserve_rtlfiles = True
         # Enable debug messages
         #d.DEBUG = True
         # Run simulations in interactive modes to monitor progress/results

inverter/controller.py

@@ -12,7 +12,8 @@ class controller(rtl):
     def _classfile(self):
         return os.path.dirname(os.path.realpath(__file__)) + "/"+__name__
 
-    def __init__(self,*arg): 
+    def __init__(self,*arg,**kwargs): 
+        self.lang=kwargs.get('lang','sv')
         self.proplist = [ 'Rs' ];    #properties that can be propagated from parent
         self.Rs = 100e6;                   # Sampling frequency
         self.step=int(1/(self.Rs*1e-12))   #Time increment for control
@@ -39,14 +40,18 @@ def __init__(self,*arg):
 
         # We now where the rtl file is. 
         # Let's read in the file to have IOs defined
-        self.dut=verilog_module(file=self.vlogsrcpath 
-                + '/inverter.sv')
+        if self.lang == 'sv':
+            self.dut=verilog_module(file=self.vlogsrcpath 
+                    + '/inverter.sv')
+        elif self.lang == 'vhdl':
+            self.dut=vhdl_entity(file=self.vhdlsrcpath 
+                    + '/inverter.vhd')
 
         # Define the signal connectors associated with this 
         # controller
         # These are signals of tb driving several targets
         # Not present in DUT
-        self.connectors=rtl_connector_bundle()
+        self.connectors=rtl_connector_bundle(lang=self.lang)
 
         if len(arg)>=1:
             parent=arg[0]
@@ -81,6 +86,7 @@ def init(self):
     def reset_control_sequence(self):
         f=self.iofile_bundle.Members['control_write']
         self.time=0
+        # IO is a file data stuctur
         f.Data= np.array([])
         f.set_control_data(init=0) # Initialize to zeros at time 0
         self.assign_io()
@@ -99,15 +105,16 @@ def define_control(self):
         for name, val in self.signallist_write:
             # We manipulate connectors as rtl_iofile operate on those
             if name in self.newsigs_write:
-                self.connectors.new(name=name, cls='reg')
+                #Type is needed for vhdl
+                self.connectors.new(name=name, cls='reg', type='std_logic')
             else:
                 self.connectors.Members[name]=self.dut.io_signals.Members[name]
                 self.connectors.Members[name].init=''
             scansigs_write.append(name) 
 
         f=self.iofile_bundle.Members['control_write']
         #define connectors controlled by this file in order of the list provided 
-        f.verilog_connectors=self.connectors.list(names=scansigs_write)
+        f.rtl_connectors=self.connectors.list(names=scansigs_write)
         f.set_control_data(init=0) # Initialize to zeros at time 0
 
     #Methods to reset and to start datafeed