USRT

USRT is a UART-like serial peripheral connected to an APB bus, implemented in Verilog.

The project was built as a small digital design exercise around three pieces working together:

• an APB-facing register interface
• a configurable serial transmit / receive path
• simulation testbenches for the individual modules and the integrated top-level design

Overview

The top-level module in src/top.v connects the bus interface, status/config register, baud-rate generator, transmit path, and receive path into a single peripheral.

The peripheral exposes three APB-visible register targets through i_Paddr[31:30]:

• 00: status / control register
• 01: transmit data register
• 10: receive data register

The status/control register stores:

• transmit busy flag
• receive-full flag
• parity configuration
• baud-rate selection

The implemented baud presets are:

• 1200
• 2400
• 4800
• 9600
• 19200
• 38400
• 57600
• 115200

Design Structure

Main modules in src/:

• top.v: full peripheral integration
• busint.v: APB address decode and enable generation
• statusreg.v: control register, status bits, parity selection, baud selection
• baudgen.v: baud clock generation
• txdatreg.v: transmit data register and ready/busy handshake
• txparity.v: transmit frame generation with parity
• txshift.v: parallel-to-serial transmit shift register
• rxshift.v: serial-to-parallel receive shift register
• rxparity.v: parity checking and received byte extraction
• rxdatreg.v: receive data register with full flag

Testbenches are also included in src/, for example:

• test_top.v: integrated peripheral test
• test_tx.v, test_rx.v: transmit / receive path tests
• test_bus.v, test_busint.v: APB-side tests

Data Flow

Transmit

1. The CPU writes control bits to the status register.
2. The CPU writes one byte to the transmit register.
3. txparity.v builds the serial frame.
4. txshift.v shifts the frame out on the serial line using the generated baud clock.
5. Status bits expose the busy/ready state back to the bus side.

Receive

1. rxshift.v detects a start bit and samples the incoming serial line.
2. rxparity.v checks parity and extracts the received byte.
3. rxdatreg.v stores the byte and raises the receive-full status bit.
4. The CPU polls the status register and reads the receive register when data is available.

Simulation

The repository includes module-level and top-level testbenches. The integrated example is src/test_top.v.

Example flow with Icarus Verilog:

cd src
iverilog -o test_top.out test_top.v
vvp test_top.out
gtkwave test.vcd

The top-level testbench does the following:

• resets the peripheral
• writes the status/control register
• sends one transmit byte
• injects one received serial frame
• polls the status register for new data
• reads the receive register

Waveform Examples

Transmit Path

The transmit path loads one byte through the APB side, builds the serial frame, and shifts it out using the configured baud clock.

Receive Path

The receive path samples the serial input, reconstructs the frame, validates parity, and stores the received byte in the RX data register.

Status Polling

The integrated testbench polls the status register until the receive-full flag is raised, then reads the received byte from the RX register.

Screenshots

The images/ directory contains diagrams and waveform screenshots for the design, including:

• APB-side behavior
• baud generation
• transmit flow
• receive flow
• parity/status handling
• the overall circuit diagram

Those images are meant to complement the source by showing the module interactions and simulation behavior.

Notes

• This is a learning project, not a production UART core.
• The implementation is intentionally split into small modules so the bus logic, framing, and shift-register logic can be tested separately.
• Naming follows the original project as-is, including USRT.