TerosHDL Configuration (VS Code Extension)

The following steps outline the configuration of the TerosHDL extension within VS Code to format and lint SystemVerilog code using Verible and Verilator, respectively.

The paths to Verible and Verilator may be different, depending on which server you are using. The instructions below will assume you are using treb06/treb07 servers.

Instructions

After connecting to a server using the Remote-SSH extension in VS Code, install TerosHDL extension. Make sure it is installed "in the server" and not just locally.

Once it is installed, click the Teros icon on the left sidebar, followed by Open Global Settings Menu:

Configure the settings as follows.

NOTE: You are not required to use these settings! They are just a good place to start and should closely resemble Dr. Stitt's configuration used during lecture.

• Select the Formatter settings tab. Set Verilog/SV formatter to Verible
• Select the Formatter -> Verible settings tab. In the "Extra args" field, enter the following:
  • --indentation_spaces=4 --column_limit=110 --named_parameter_alignment=align --named_port_alignment=align --port_declarations_alignment=align --module_net_variable_alignment=align --formal_parameters_alignment=infer --module_net_variable_alignment=infer
• Select the Linter settings tab. Set Verilog/SV linter to Verilator.
• Select the Tools -> Verible tab. Set the installation path to /apps/reconfig/tools/verible/current/bin
• Select the Tools -> Verilator tab. Set the installation path to /apps/reconfig/tools/verilator/current/bin

Finally, at the bottom, select Apply and close. You may get some output at the bottom of your VS Code window saying some checks failed, but as long as Verible and Verilator checks passed, then they should work.

To format the currently opened document using Verible, you can use the Alt+Shift+F shortcut.

Verilator should run lint checks when SystemVerilog files are opened or saved.