FFTW Support#219
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FinnWilkinson merged 51 commits intodevfrom Mar 30, 2022
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Need to fix CI failure but code looks good
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…ests. Also accommodated for the alias of ROR to RORV.
…truction and tests. Created new helper function for this instruction's logic, and also accommodated for its alias.
…uction with tests.
…with tests. New helper function created for this instruction.
…sts. Also implemented the 8 and 16-bit versions of the sve DUP (scalar) sve instructions.
…e instruction with tests.
…instruction with tests and new helper function.
…ated) sve instruction with tests.
…to 3 vectors, instead of loading 3 interleaved vectors from memory.
…ented the 64-bit version of the fcadd sve instruction with tests.
…y) to verify its implementation against a real hardware run.
Implemented the 64-bit version of the FCMLA (predicated) sve instruction with tests.
…scaled) sve instructions where the Z-reg memory operand was not detected correctly at decode.
…all account for the different change types.
…REG_CNTVCT_EL0 to the iteration count (ticks completed) in main. Removed old getUpdateState function from Architecture files as now redundant.
…struction with tests and new helper function.
…ruction with tests and new helper function.
…ruction with tests and new helper function.
…nstruction with tests.
…TVCT updating according to said frequencies.
…is can cause undefined behaviour.
…re being set for instructions with 2 memory register operands (base register and index register).
…per function and tests.
…nd new helper function.
…ixed LD2D, LD3D, ST2D operand parsing in InstructionMetadata.cc, and changed max number of destination registers to 4.
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This PR mainly contains more instruction implementations from the Armv8+sve ISA to support the FFTW binary. It also includes other minor updates, the most notable of which are :