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Update AArch64 Contiguous NEON/SVE Loads#330

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jj16791 merged 2 commits intodevfrom
sve-contig-load-fix
Jul 14, 2023
Merged

Update AArch64 Contiguous NEON/SVE Loads#330
jj16791 merged 2 commits intodevfrom
sve-contig-load-fix

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@FinnWilkinson
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All single structure, contiguous vector loads (both NEON and SVE) have been adapted to generate a sigle address rather than one per element.

This change is largely motivated by a lack of accuracy to real hardware when simulating with SimEng-SST. Functionally, the instructions have not been altered.

@FinnWilkinson FinnWilkinson added the enhancement New feature or request label Jul 14, 2023
@FinnWilkinson FinnWilkinson self-assigned this Jul 14, 2023
Comment thread src/include/simeng/arch/aarch64/Instruction.hh
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
Comment thread src/lib/arch/aarch64/Instruction_address.cc
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Looks good! Just a few redundant static_casts

Comment thread src/include/simeng/MemoryInterface.hh
@jj16791 jj16791 merged commit c42eea3 into dev Jul 14, 2023
@FinnWilkinson FinnWilkinson deleted the sve-contig-load-fix branch October 26, 2023 08:20
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