signal of type 'subtype is not recognized and gives an error

[rugebiker]

Hi,
If I have in the architecture body these signal declarations:

signal hello : std_logic_vector(7 downto 0);
signal world : hello'subtype;

VHDL-LS gives an error on the tick ( ' ) saying: Expected ';'

The expectation would be that no error is given. As a side note, 'subtype is a VHDL-2008 feature.
Thanks!

[kraigher]

I fixed this now, better late then never.