fix formatting of block statements

[rossmeier]

Thanks so much for this project!

Here is a little problem + fix I found using vhdl blocks

Before:

b_bla: block is
    signal s1: std_logic;
    signal s2: std_logic;
begin

    s1 <= s2;end block;

After:

b_bla: block is
    signal s1: std_logic;
    signal s2: std_logic;
begin
    s1 <= s2;
end block;

I cross referenced with how this is solved for process and it seems alright to me now.

[Schottkyc137]

Thanks for the fix!