Flash bitstream via miob controller

[stv0g]

/cc @n-eiling @iripiri

See:

• https://villas.fein-aachen.org/docs/controller/protocol#start
• https://git.rwth-aachen.de/acs/public/villas/controller/-/blob/master/villas/controller/components/managers/miob.py

@n-eiling Could you provide the required command for flashing a bitstream to the FPGA?

Is there maybe also a way to retrieve the status of the FPGA via XSDB? Those commands would also be useful, so we can display the FPGA status as well.

[stv0g]

I think I forgot the most import piece here:

The idea is to treat the bitstream of a MIOB component in the same way as a model file for a simulator component.

[stv0g]

In GitLab by @n-eiling on May 10, 2022, 12:04

https://github.com/RWTH-ACS/miob/blob/main/sw/hw_server/fpga_program.service