add support for VHDL-2019 interfaces for QuestaSim

[Ahmad-Zaklouta]

The latest QuestaSim from Intel started to support interfaces but latest Vunit doesn't work with that.

It seems the problem is with this line:

vunit/vunit/sim_if/modelsim.py

Line 180 in 4090eb5

if vhdl_standard <= VHDL.STD_2008:

my work around is to change 2008 to 2019 and I have tested and simulate with it. not sure though if this break anything.

[LarsAsplund]

@Ahmad-Zaklouta As I'm approaching v5.0.0, I will also review the current simulator status when it comes to 2019 support. There are two aspects of this. One is if they support 2019 at all and the other is if they support the 2019 features VUnit provides. I was waiting for my client to update their Questa version to test this but now that Intel updated their Questa variant, I can proceed directly.

Note that VUnit uses the 2008 standard by default but as long as we've enabled 2019 for Questa you can change this: https://vunit.github.io/cli.html#language-revision-selection

[LarsAsplund]

@Ahmad-Zaklouta Please check #1170

[Ahmad-Zaklouta]

now it is working thanks