fix docs egs

examples/verilog/uart/run.py

@@ -15,15 +15,14 @@
 from os.path import join, dirname
 from vunit.verilog import VUnit
 
-ui = VUnit.from_argv()
+vu = VUnit.from_argv()
 
 src_path = join(dirname(__file__), "src")
 
-uart_lib = ui.add_library("uart_lib")
+uart_lib = vu.add_library("uart_lib")
 uart_lib.add_source_files(join(src_path, "*.sv"))
 
-tb_uart_lib = ui.add_library("tb_uart_lib")
+tb_uart_lib = vu.add_library("tb_uart_lib")
 tb_uart_lib.add_source_files(join(src_path, "test", "*.sv"))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/verilog/user_guide/run.py

@@ -17,9 +17,8 @@
 
 root = dirname(__file__)
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
+vu = VUnit.from_argv()
+lib = vu.add_library("lib")
 lib.add_source_files(join(root, "*.sv"))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/verilog/verilog_ams/run.py

@@ -9,10 +9,9 @@
 
 root = dirname(__file__)
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
+vu = VUnit.from_argv()
+lib = vu.add_library("lib")
 lib.add_source_files(join(root, "*.sv"))
 lib.add_source_files(join(root, "*.vams")).set_compile_option("modelsim.vlog_flags", ["-ams"])
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/array/run.py

@@ -18,12 +18,15 @@
 
 root = dirname(__file__)
 
-ui = VUnit.from_argv()
-ui.add_osvvm()
-ui.add_array_util()
-lib = ui.add_library("lib")
-lib.add_source_files(join(root, "src", "*.vhd"))
-lib.add_source_files(join(root, "src", "test", "*.vhd"))
-
-if __name__ == '__main__':
-    ui.main()
+vu = VUnit.from_argv()
+vu.add_osvvm()
+vu.add_array_util()
+
+src_path = join(dirname(__file__), 'src')
+
+vu.add_library('lib').add_source_files([
+    join(src_path, '*.vhd'),
+    join(src_path, 'test', '*.vhd')
+])
+
+vu.main()

examples/vhdl/array_axis_vcs/run.py

@@ -21,19 +21,19 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-root = dirname(__file__)
-
 vu = VUnit.from_argv()
 
 vu.add_osvvm()
 vu.add_array_util()
 vu.add_verification_components()
 
-lib = vu.add_library("lib")
-lib.add_source_files(join(root, "src/*.vhd"))
-lib.add_source_files(join(root, "src/**/*.vhd"))
+src_path = join(dirname(__file__), "src")
+
+vu.add_library("lib").add_source_files([
+    join(src_path, "*.vhd"),
+    join(src_path, "**", "*.vhd")
+])
 
 # vu.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
 
-if __name__ == '__main__':
-    vu.main()
+vu.main()

examples/vhdl/axi_dma/run.py

@@ -18,15 +18,15 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-ui = VUnit.from_argv()
-ui.add_osvvm()
-ui.add_verification_components()
+vu = VUnit.from_argv()
+vu.add_osvvm()
+vu.add_verification_components()
 
 src_path = join(dirname(__file__), "src")
 
-axi_dma_lib = ui.add_library("axi_dma_lib")
-axi_dma_lib.add_source_files(join(src_path, "*.vhd"))
-axi_dma_lib.add_source_files(join(src_path, "test", "*.vhd"))
+vu.add_library("axi_dma_lib").add_source_files([
+    join(src_path, "*.vhd"),
+    join(src_path, "test", "*.vhd")
+])
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/check/run.py

@@ -14,18 +14,16 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-ui = VUnit.from_argv()
+vu = VUnit.from_argv()
 
 # Enable location preprocessing but exclude all but check_false to make the example less bloated
-ui.enable_location_preprocessing(
+vu.enable_location_preprocessing(
     exclude_subprograms=['debug', 'info', 'check', 'check_failed', 'check_true', 'check_implication',
                          'check_stable', 'check_equal', 'check_not_unknown', 'check_zero_one_hot',
                          'check_one_hot', 'check_next', 'check_sequence', 'check_relation'])
 
-ui.enable_check_preprocessing()
+vu.enable_check_preprocessing()
 
-lib = ui.add_library("lib")
-lib.add_source_files(join(dirname(__file__), "tb_example.vhd"))
+vu.add_library("lib").add_source_files(join(dirname(__file__), "tb_example.vhd"))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/com/run.py

@@ -16,16 +16,12 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-prj = VUnit.from_argv()
-prj.add_com()
-prj.add_verification_components()
-prj.add_osvvm()
+vu = VUnit.from_argv()
+vu.add_com()
+vu.add_verification_components()
+vu.add_osvvm()
 
-lib = prj.add_library('lib')
-lib.add_source_files(join(dirname(__file__), 'src', '*.vhd'))
+vu.add_library('lib').add_source_files(join(dirname(__file__), 'src', '*.vhd'))
+vu.add_library('tb_lib').add_source_files(join(dirname(__file__), 'test', '*.vhd'))
 
-tb_lib = prj.add_library('tb_lib')
-tb_lib.add_source_files(join(dirname(__file__), 'test', '*.vhd'))
-
-if __name__ == '__main__':
-    prj.main()
+vu.main()

examples/vhdl/composite_generics/run.py

@@ -14,24 +14,22 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-prj = VUnit.from_argv()
 
-tb_lib = prj.add_library('tb_lib')
-tb_lib.add_source_files(join(dirname(__file__), 'test', '*.vhd'))
+def encode(tb_cfg):
+    return ", ".join(["%s:%s" % (key, str(tb_cfg[key])) for key in tb_cfg])
 
-testbench = tb_lib.test_bench("tb_composite_generics")
-test_1 = testbench.test("Test 1")
 
+vu = VUnit.from_argv()
 
-def encode(tb_cfg):
-    return ", ".join(["%s:%s" % (key, str(tb_cfg[key])) for key in tb_cfg])
+tb_lib = vu.add_library('tb_lib')
+tb_lib.add_source_files(join(dirname(__file__), 'test', '*.vhd'))
 
+test_1 = tb_lib.test_bench("tb_composite_generics").test("Test 1")
 
 vga_tb_cfg = dict(image_width=640, image_height=480, dump_debug_data=False)
 test_1.add_config(name='VGA', generics=dict(encoded_tb_cfg=encode(vga_tb_cfg)))
 
 tiny_tb_cfg = dict(image_width=4, image_height=3, dump_debug_data=True)
 test_1.add_config(name='tiny', generics=dict(encoded_tb_cfg=encode(tiny_tb_cfg)))
 
-if __name__ == '__main__':
-    prj.main()
+vu.main()

examples/vhdl/coverage/run.py

@@ -7,20 +7,20 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-root = dirname(__file__)
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
-lib.add_source_files(join(root, "*.vhd"))
+def post_run(results):
+    results.merge_coverage(file_name="coverage_data")
+
+
+vu = VUnit.from_argv()
+
+lib = vu.add_library("lib")
+lib.add_source_files(join(dirname(__file__), "*.vhd"))
 
 lib.set_compile_option("rivierapro.vcom_flags", ["-coverage", "bs"])
 lib.set_compile_option("rivierapro.vlog_flags", ["-coverage", "bs"])
 lib.set_compile_option("modelsim.vcom_flags", ["+cover=bs"])
 lib.set_compile_option("modelsim.vlog_flags", ["+cover=bs"])
 lib.set_sim_option("enable_coverage", True)
 
-def post_run(results):
-    results.merge_coverage(file_name="coverage_data")
-
-if __name__ == '__main__':
-    ui.main(post_run=post_run)
+vu.main(post_run=post_run)

examples/vhdl/generate_tests/run.py

@@ -54,17 +54,19 @@ def generate_tests(obj, signs, data_widths):
         config_name = "data_width=%i,sign=%s" % (data_width, sign)
 
         # Add the configuration with a post check function to verify the output
-        obj.add_config(name=config_name,
-                       generics=dict(
-                           data_width=data_width,
-                           sign=sign),
-                       post_check=make_post_check(data_width, sign))
+        obj.add_config(
+            name=config_name,
+            generics=dict(
+                data_width=data_width,
+                sign=sign),
+            post_check=make_post_check(data_width, sign)
+        )
 
 
 test_path = join(dirname(__file__), "test")
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
+vu = VUnit.from_argv()
+lib = vu.add_library("lib")
 lib.add_source_files(join(test_path, "*.vhd"))
 
 tb_generated = lib.test_bench("tb_generated")
@@ -81,5 +83,4 @@ def generate_tests(obj, signs, data_widths):
         # Run all other tests with signed/unsigned and data width in range [1,5[
         generate_tests(test, [False, True], range(1, 5))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/json4vhdl/run.py

@@ -19,15 +19,12 @@
 root = dirname(__file__)
 
 vu = VUnit.from_argv()
-
 vu.add_json4vhdl()
 
-lib = vu.add_library("test")
-lib.add_source_files(join(root, "src/test/*.vhd"))
+vu.add_library("test").add_source_files(join(root, "src/test/*.vhd"))
 
 tb_cfg = read_json(join(root, "src/test/data/data.json"))
 tb_cfg["dump_debug_data"]=False
 vu.set_generic("tb_cfg", encode_json(tb_cfg))
 
-if __name__ == '__main__':
-    vu.main()
+vu.main()

examples/vhdl/logging/run.py

@@ -14,9 +14,7 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
-lib.add_source_files(join(dirname(__file__), "*.vhd"))
+vu = VUnit.from_argv()
+vu.add_library("lib").add_source_files(join(dirname(__file__), "*.vhd"))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/run/run.py

@@ -16,11 +16,11 @@
 
 root = dirname(__file__)
 
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
+vu = VUnit.from_argv()
+
+lib = vu.add_library("lib")
 lib.add_source_files(join(root, "*.vhd"))
 tb_with_lower_level_control = lib.entity("tb_with_lower_level_control")
 tb_with_lower_level_control.scan_tests_from_file(join(root, "test_control.vhd"))
 
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/third_party_integration/run.py

@@ -7,11 +7,6 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-root = dirname(__file__)
-ui = VUnit.from_argv()
-
-lib = ui.add_library("lib")
-lib.add_source_files(join(root, 'test', '*.vhd'))
-
-if __name__ == '__main__':
-    ui.main()
+vu = VUnit.from_argv()
+vu.add_library("lib").add_source_files(join(dirname(__file__), 'test', '*.vhd'))
+vu.main()

examples/vhdl/uart/run.py

@@ -15,17 +15,13 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-ui = VUnit.from_argv()
-ui.add_osvvm()
-ui.add_verification_components()
+vu = VUnit.from_argv()
+vu.add_osvvm()
+vu.add_verification_components()
 
 src_path = join(dirname(__file__), "src")
 
-uart_lib = ui.add_library("uart_lib")
-uart_lib.add_source_files(join(src_path, "*.vhd"))
+vu.add_library("uart_lib").add_source_files(join(src_path, "*.vhd"))
+vu.add_library("tb_uart_lib").add_source_files(join(src_path, "test", "*.vhd"))
 
-tb_uart_lib = ui.add_library("tb_uart_lib")
-tb_uart_lib.add_source_files(join(src_path, "test", "*.vhd"))
-
-if __name__ == '__main__':
-    ui.main()
+vu.main()

examples/vhdl/user_guide/run.py

@@ -15,11 +15,6 @@
 from os.path import join, dirname
 from vunit import VUnit
 
-root = dirname(__file__)
-
-ui = VUnit.from_argv()
-lib = ui.add_library("lib")
-lib.add_source_files(join(root, "*.vhd"))
-
-if __name__ == '__main__':
-    ui.main()
+vu = VUnit.from_argv()
+vu.add_library("lib").add_source_files(join(dirname(__file__), "*.vhd"))
+vu.main()

examples/vhdl/vivado/run.py

@@ -16,20 +16,18 @@
 from vunit import VUnit
 from vivado_util import add_vivado_ip
 
-ui = VUnit.from_argv()
-
 root = dirname(__file__)
 src_path = join(root, "src")
 
-lib = ui.add_library("lib")
-lib.add_source_files(join(src_path, "*.vhd"))
+vu = VUnit.from_argv()
 
-tb_lib = ui.add_library("tb_lib")
-tb_lib.add_source_files(join(src_path, "test", "*.vhd"))
+vu.add_library("lib").add_source_files(join(src_path, "*.vhd"))
+vu.add_library("tb_lib").add_source_files(join(src_path, "test", "*.vhd"))
 
-if __name__ == '__main__':
-    add_vivado_ip(ui,
-                  output_path=join(root, "vivado_libs"),
-                  project_file=join(root, "myproject", "myproject.xpr"))
+add_vivado_ip(
+    vu,
+    output_path=join(root, "vivado_libs"),
+    project_file=join(root, "myproject", "myproject.xpr")
+)
 
-    ui.main()
+vu.main()