GitHub - ValDLaw/MultiCycle

iverilog -o arm_multi.out -c arm_multi.txt vvp .\arm_multi.out gtkwave arm_multi.vcd

Name		Name	Last commit message	Last commit date
Latest commit History 38 Commits
.gitignore		.gitignore
README.md		README.md
alu.v		alu.v
arm.v		arm.v
arm_multi.txt		arm_multi.txt
arm_multi.v		arm_multi.v
condcheck.v		condcheck.v
condlogic.v		condlogic.v
controller.v		controller.v
controller_tb.v		controller_tb.v
datapath.v		datapath.v
decode.v		decode.v
extend.v		extend.v
flopenr.v		flopenr.v
flopr.v		flopr.v
formato_inv.md		formato_inv.md
fsm.v		fsm.v
mem.v		mem.v
memfile.dat		memfile.dat
mux2.v		mux2.v
mux3.v		mux3.v
regfile.v		regfile.v
testbench.v		testbench.v
top.v		top.v

Provide feedback