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MSVC shows several warnings, but this one is shown as an error, preventing compilation.

error C4146: unary minus operator applied to unsigned type, result still unsigned

MSVC shows several warnings, but this one is shown as an error, preventing compilation.
@galenbwill galenbwill self-assigned this May 7, 2025
@galenbwill galenbwill added Component: Architecture Issue needs changes to an architecture plugin Arch: ARM64 Issues with the AArch64 architecture plugin Impact: Medium Issue is impactful with a bad, or no, workaround Effort: Trivial Issues require < 1 day of work Type: DX labels May 7, 2025
@galenbwill galenbwill added this to the Helion milestone May 7, 2025
@galenbwill galenbwill merged commit d5080db into Vector35:dev May 27, 2025
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Unfortunately, I had to revert this commit as it broke the arm64test.py output for BFI. For example:

LIFT MISMATCH AT TEST 3157!
           input: c31d1c33 bfi     w3, w14, #0xffffffe4, #0x8
            test: 331C1DC3 bfi w3, w14, #0xffffffe4, #0x8
        expected: LLIL_SET_REG.d(w3,LLIL_OR.d(LLIL_AND.d(LLIL_CONST.d(0xFFFFF00F),LLIL_REG.d(w3)),LLIL_LSL.d(LLIL_AND.d(LLIL_CONST.d(0xFF),LLIL_REG.d(w14)),LLIL_CONST.b(0x4))))
          actual: LLIL_SET_REG.d(w3,LLIL_OR.d(LLIL_AND.d(LLIL_CONST.d(-0xFEF00000001),LLIL_REG.d(w3)),LLIL_LSL.d(LLIL_AND.d(LLIL_CONST.d(0xFF),LLIL_REG.d(w14)),LLIL_CONST.b(0xFFFFFFE4))))
            tree:
LLIL_SET_REG.d
    w3
    LLIL_OR.d
        LLIL_AND.d
            LLIL_CONST.d
                -0xFEF00000001
            LLIL_REG.d
                w3
        LLIL_LSL.d
            LLIL_AND.d
                LLIL_CONST.d
                    0xFF
                LLIL_REG.d
                    w14
            LLIL_CONST.b
                0xFFFFFFE4

After some closer investigation, it also turns out that this change causes the disassembly output to be incorrect, and the LLIL to be lifted incorrectly:

Before/After this patch:

Disassembly:

c31d1c33   bfi     w3, w14, #0x4, #8
c31d1c33   bfi     w3, w14, #0xffffffe4, #0x8

LLIL:

w3 = (-0xff1 & w3) | (0xff & w14) << 4
w3 = (-0xff000000001 & w3) | (0xff & w14) << 0xffffffe4

MLIL:

x3 = zx.q((0xfffff00f & arg4) | zx.d(arg5) << 4)
x3 = zx.q((0xffffffff & arg4) | zx.d(arg5) << 0xe4)

I have also verified that the original code does not cause a warning on the version of MSVC we use in our build infrastructure. Also, from the link you posted above, it sounds like the problem might be a bug in the version of MSVC you're using.

Try adding #pragma warning(disable:4146) right above the offending line and see if that prevents the error.

@justanotheranonymoususer
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@galenbwill
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I actually did try exactly that code when I was investigating, and yes, it does pass the tests and seems to result in semantically correct decompilation.

If you update the PR, I will merge it the next time I'm pushing another change (which will probably be in the next day or so).

@justanotheranonymoususer justanotheranonymoususer deleted the patch-1 branch May 28, 2025 21:59
@justanotheranonymoususer
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Actually the pragma works too and it's less ugly. Created #6896

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Arch: ARM64 Issues with the AArch64 architecture plugin Component: Architecture Issue needs changes to an architecture plugin Effort: Trivial Issues require < 1 day of work Impact: Medium Issue is impactful with a bad, or no, workaround

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