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Venus-Lv5/README.md

HI 👋👋👋

I'm Vo Quang Huy (aka Venus) I'm a student majoring in Computer Engineering Technology at HCMUTE and I aspire to become an IC Design Engineer (specifically IC Design Verification Engineering). I find myself interested in Verilog/SystemVerilog, UVM, and some related technologies I regularly share my projects to showcase my progress. Feel free to explore them if you're interested.

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Favorite Project

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  1. Design_and_Verification_SPI_master_IP Design_and_Verification_SPI_master_IP Public

    Design IP SPI master and verification using UVM

    SystemVerilog 1

  2. UART_VIP_Verification UART_VIP_Verification Public

    UART VIP Verification using UVM

    SystemVerilog 1

  3. UART_VIP_Validate UART_VIP_Validate Public

    Develop and validate UART VIP

    SystemVerilog