This Project is to demonstrate the flow of RTL file until synthesis.
It helps compile and simulate the verilog design file using a predefined testbench to ensure the functionality of the design matches the specific requirement.
Outputs
- Binary/Executable file
- vvp simulation
- GTKWave
Generates a coverage report for verilog Test bench and Design file.
- The purpose of running coverage analysis is to see how much of our design was tested by the provided testbench.
- Coverage analysis can help pinpoint untested areas in our design, such as missed conditions in a case statement, unused branches, or skipped paths in combinational or sequential logic.
Outputs:
- Coverage Data Dump file
- Coverage Report
The yosys tool is to synthesize the design file (after simulation) to a netlist with actual modules and devices from a technology library (PDK) that will resemble the operation of the requirement.
It takes design file and technology library as input files and uses them to generate the netlist.
It first converts high-level behavioral logic to a lower-level gate representation
Then maps the gates to internal cell library (ABC library).
Further it maps these combinational and sequential circuits to their respective cells and devices from the PDK.
After cleaning the unnecessary connections and devices the yosys tool generates the report of the design and will contain important details about the design.
Lastly, a netlist file is generated that will have the actual connections of each and every device used in our design.
Outputs:
- Statistics
