Skip to content

SIMD #1820

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
tlively merged 37 commits into from
Dec 14, 2018
Merged

SIMD #1820

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
37 commits
Select commit Hold shift + click to select a range
4615f3b
V128 Literals and operations
tlively Nov 28, 2018
874addf
Move makeLiteralFromInt32 and makeLiteralZero to literal.h
tlively Dec 4, 2018
19b44ed
Finish implementing SIMD literal ops
tlively Dec 4, 2018
b2f5c56
Implement lots of SIMD visitors all over the place
tlively Dec 4, 2018
fa2e5a5
Add SIMD Expression IDs to API
tlively Dec 4, 2018
9bbe9e0
REVERT ME: allow all sizes of float loads (what's going on with safe-…
tlively Dec 4, 2018
4fdb5ba
Revert "REVERT ME: allow all sizes of float loads (what's going on wi…
tlively Dec 4, 2018
24aa1cd
V128 literal parsing
tlively Dec 4, 2018
f1f6b12
Fix SafeHeap bug and add v128 support
tlively Dec 4, 2018
cedacd4
Add simd test and fix print bug
tlively Dec 4, 2018
20fb55f
Fix parsing bugs
tlively Dec 4, 2018
f15ba6d
Fix parser error mixing up Le/Gt simd comparisons
tlively Dec 4, 2018
f24ad1d
UPDATE ME: add stuff to blacklisted memory.wast file
tlively Dec 4, 2018
bb947f7
Start spec tests, implement v128 load/store interpretation
tlively Dec 4, 2018
9de5ddd
More tests and bug fixes
tlively Dec 5, 2018
c4ae8e9
Finish comparison tests and make comparisons emit masks
tlively Dec 5, 2018
9929157
Fix saturating arithmetic
tlively Dec 6, 2018
4822fe2
Finish i16x8 arithmetic
tlively Dec 6, 2018
0319bf2
Test through i32x4 arithmetic and fix shifts
tlively Dec 6, 2018
e662229
Finish spec tests and fix conversions
tlively Dec 6, 2018
3e56e84
Fix i63x4 in print
tlively Dec 6, 2018
48ac9c6
Fix comparison binary parsing bug
tlively Dec 6, 2018
5f6aec3
Add builder and C apis
tlively Dec 6, 2018
f63b80f
Upgrade tracing and finish kitchen sink C tests
tlively Dec 11, 2018
b4501a6
JS API, C API accessors, and testing
tlively Dec 12, 2018
b964f07
Remove repeated tests from memory.wast
tlively Dec 12, 2018
3b18385
Add extra curlies to make clang 5.0.0 happy
tlively Dec 12, 2018
4d88447
Explicitly initialize some vars to help gcc out
tlively Dec 12, 2018
dc16d00
Remove obsolete sat_add function
tlively Dec 13, 2018
e9ff225
Update js tests
tlively Dec 13, 2018
c8de9e0
address first batch of comments
tlively Dec 13, 2018
69904cd
Argument evaluation order is unspecified. obviously.
tlively Dec 13, 2018
f15dc01
Merge branch 'master' into minimal-literal
tlively Dec 13, 2018
78baf29
More arg evaluation order fixes
tlively Dec 13, 2018
9e541b8
Add SIMD feature options and make SafeHeap feature-aware
tlively Dec 13, 2018
44e19ad
make parameter to `getBits` a reference to array of bytes
tlively Dec 13, 2018
dc893cb
Remove extraneous "shift" operation
tlively Dec 14, 2018
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
172 changes: 172 additions & 0 deletions build-js.sh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,11 @@ export_function "_BinaryenAtomicCmpxchgId"
export_function "_BinaryenAtomicRMWId"
export_function "_BinaryenAtomicWaitId"
export_function "_BinaryenAtomicWakeId"
export_function "_BinaryenSIMDExtractId"
export_function "_BinaryenSIMDReplaceId"
export_function "_BinaryenSIMDShuffleId"
export_function "_BinaryenSIMDBitselectId"
export_function "_BinaryenSIMDShiftId"

# External kinds
export_function "_BinaryenExternalFunction"
Expand All @@ -226,6 +231,7 @@ export_function "_BinaryenLiteralInt32"
export_function "_BinaryenLiteralInt64"
export_function "_BinaryenLiteralFloat32"
export_function "_BinaryenLiteralFloat64"
export_function "_BinaryenLiteralVec128"
export_function "_BinaryenLiteralFloat32Bits"
export_function "_BinaryenLiteralFloat64Bits"

Expand Down Expand Up @@ -374,6 +380,141 @@ export_function "_BinaryenAtomicRMWAnd"
export_function "_BinaryenAtomicRMWOr"
export_function "_BinaryenAtomicRMWXor"
export_function "_BinaryenAtomicRMWXchg"
export_function "_BinaryenSplatVecI8x16"
export_function "_BinaryenExtractLaneSVecI8x16"
export_function "_BinaryenExtractLaneUVecI8x16"
export_function "_BinaryenReplaceLaneVecI8x16"
export_function "_BinaryenSplatVecI16x8"
export_function "_BinaryenExtractLaneSVecI16x8"
export_function "_BinaryenExtractLaneUVecI16x8"
export_function "_BinaryenReplaceLaneVecI16x8"
export_function "_BinaryenSplatVecI32x4"
export_function "_BinaryenExtractLaneVecI32x4"
export_function "_BinaryenReplaceLaneVecI32x4"
export_function "_BinaryenSplatVecI64x2"
export_function "_BinaryenExtractLaneVecI64x2"
export_function "_BinaryenReplaceLaneVecI64x2"
export_function "_BinaryenSplatVecF32x4"
export_function "_BinaryenExtractLaneVecF32x4"
export_function "_BinaryenReplaceLaneVecF32x4"
export_function "_BinaryenSplatVecF64x2"
export_function "_BinaryenExtractLaneVecF64x2"
export_function "_BinaryenReplaceLaneVecF64x2"
export_function "_BinaryenEqVecI8x16"
export_function "_BinaryenNeVecI8x16"
export_function "_BinaryenLtSVecI8x16"
export_function "_BinaryenLtUVecI8x16"
export_function "_BinaryenGtSVecI8x16"
export_function "_BinaryenGtUVecI8x16"
export_function "_BinaryenLeSVecI8x16"
export_function "_BinaryenLeUVecI8x16"
export_function "_BinaryenGeSVecI8x16"
export_function "_BinaryenGeUVecI8x16"
export_function "_BinaryenEqVecI16x8"
export_function "_BinaryenNeVecI16x8"
export_function "_BinaryenLtSVecI16x8"
export_function "_BinaryenLtUVecI16x8"
export_function "_BinaryenGtSVecI16x8"
export_function "_BinaryenGtUVecI16x8"
export_function "_BinaryenLeSVecI16x8"
export_function "_BinaryenLeUVecI16x8"
export_function "_BinaryenGeSVecI16x8"
export_function "_BinaryenGeUVecI16x8"
export_function "_BinaryenEqVecI32x4"
export_function "_BinaryenNeVecI32x4"
export_function "_BinaryenLtSVecI32x4"
export_function "_BinaryenLtUVecI32x4"
export_function "_BinaryenGtSVecI32x4"
export_function "_BinaryenGtUVecI32x4"
export_function "_BinaryenLeSVecI32x4"
export_function "_BinaryenLeUVecI32x4"
export_function "_BinaryenGeSVecI32x4"
export_function "_BinaryenGeUVecI32x4"
export_function "_BinaryenEqVecF32x4"
export_function "_BinaryenNeVecF32x4"
export_function "_BinaryenLtVecF32x4"
export_function "_BinaryenGtVecF32x4"
export_function "_BinaryenLeVecF32x4"
export_function "_BinaryenGeVecF32x4"
export_function "_BinaryenEqVecF64x2"
export_function "_BinaryenNeVecF64x2"
export_function "_BinaryenLtVecF64x2"
export_function "_BinaryenGtVecF64x2"
export_function "_BinaryenLeVecF64x2"
export_function "_BinaryenGeVecF64x2"
export_function "_BinaryenNotVec128"
export_function "_BinaryenAndVec128"
export_function "_BinaryenOrVec128"
export_function "_BinaryenXorVec128"
export_function "_BinaryenNegVecI8x16"
export_function "_BinaryenAnyTrueVecI8x16"
export_function "_BinaryenAllTrueVecI8x16"
export_function "_BinaryenShlVecI8x16"
export_function "_BinaryenShrSVecI8x16"
export_function "_BinaryenShrUVecI8x16"
export_function "_BinaryenAddVecI8x16"
export_function "_BinaryenAddSatSVecI8x16"
export_function "_BinaryenAddSatUVecI8x16"
export_function "_BinaryenSubVecI8x16"
export_function "_BinaryenSubSatSVecI8x16"
export_function "_BinaryenSubSatUVecI8x16"
export_function "_BinaryenMulVecI8x16"
export_function "_BinaryenNegVecI16x8"
export_function "_BinaryenAnyTrueVecI16x8"
export_function "_BinaryenAllTrueVecI16x8"
export_function "_BinaryenShlVecI16x8"
export_function "_BinaryenShrSVecI16x8"
export_function "_BinaryenShrUVecI16x8"
export_function "_BinaryenAddVecI16x8"
export_function "_BinaryenAddSatSVecI16x8"
export_function "_BinaryenAddSatUVecI16x8"
export_function "_BinaryenSubVecI16x8"
export_function "_BinaryenSubSatSVecI16x8"
export_function "_BinaryenSubSatUVecI16x8"
export_function "_BinaryenMulVecI16x8"
export_function "_BinaryenNegVecI32x4"
export_function "_BinaryenAnyTrueVecI32x4"
export_function "_BinaryenAllTrueVecI32x4"
export_function "_BinaryenShlVecI32x4"
export_function "_BinaryenShrSVecI32x4"
export_function "_BinaryenShrUVecI32x4"
export_function "_BinaryenAddVecI32x4"
export_function "_BinaryenSubVecI32x4"
export_function "_BinaryenMulVecI32x4"
export_function "_BinaryenNegVecI64x2"
export_function "_BinaryenAnyTrueVecI64x2"
export_function "_BinaryenAllTrueVecI64x2"
export_function "_BinaryenShlVecI64x2"
export_function "_BinaryenShrSVecI64x2"
export_function "_BinaryenShrUVecI64x2"
export_function "_BinaryenAddVecI64x2"
export_function "_BinaryenSubVecI64x2"
export_function "_BinaryenAbsVecF32x4"
export_function "_BinaryenNegVecF32x4"
export_function "_BinaryenSqrtVecF32x4"
export_function "_BinaryenAddVecF32x4"
export_function "_BinaryenSubVecF32x4"
export_function "_BinaryenMulVecF32x4"
export_function "_BinaryenDivVecF32x4"
export_function "_BinaryenMinVecF32x4"
export_function "_BinaryenMaxVecF32x4"
export_function "_BinaryenAbsVecF64x2"
export_function "_BinaryenNegVecF64x2"
export_function "_BinaryenSqrtVecF64x2"
export_function "_BinaryenAddVecF64x2"
export_function "_BinaryenSubVecF64x2"
export_function "_BinaryenMulVecF64x2"
export_function "_BinaryenDivVecF64x2"
export_function "_BinaryenMinVecF64x2"
export_function "_BinaryenMaxVecF64x2"
export_function "_BinaryenTruncSatSVecF32x4ToVecI32x4"
export_function "_BinaryenTruncSatUVecF32x4ToVecI32x4"
export_function "_BinaryenTruncSatSVecF64x2ToVecI64x2"
export_function "_BinaryenTruncSatUVecF64x2ToVecI64x2"
export_function "_BinaryenConvertSVecI32x4ToVecF32x4"
export_function "_BinaryenConvertUVecI32x4ToVecF32x4"
export_function "_BinaryenConvertSVecI64x2ToVecF64x2"
export_function "_BinaryenConvertUVecI64x2ToVecF64x2"

# Expression creation
export_function "_BinaryenBlock"
Expand Down Expand Up @@ -405,6 +546,11 @@ export_function "_BinaryenAtomicRMW"
export_function "_BinaryenAtomicCmpxchg"
export_function "_BinaryenAtomicWait"
export_function "_BinaryenAtomicWake"
export_function "_BinaryenSIMDExtract"
export_function "_BinaryenSIMDReplace"
export_function "_BinaryenSIMDShuffle"
export_function "_BinaryenSIMDBitselect"
export_function "_BinaryenSIMDShift"

# 'Expression' operations
export_function "_BinaryenExpressionGetId"
Expand Down Expand Up @@ -535,6 +681,32 @@ export_function "_BinaryenAtomicWaitGetExpectedType"
export_function "_BinaryenAtomicWakeGetPtr"
export_function "_BinaryenAtomicWakeGetWakeCount"

# 'SIMDExtract' expression operations
export_function "_BinaryenSIMDExtractGetOp"
export_function "_BinaryenSIMDExtractGetVec"
export_function "_BinaryenSIMDExtractGetIdx"

# 'SIMDReplace' expression operations
export_function "_BinaryenSIMDReplaceGetOp"
export_function "_BinaryenSIMDReplaceGetVec"
export_function "_BinaryenSIMDReplaceGetIdx"
export_function "_BinaryenSIMDReplaceGetValue"

# 'SIMDShuffle' expression operations
export_function "_BinaryenSIMDShuffleGetLeft"
export_function "_BinaryenSIMDShuffleGetRight"
export_function "_BinaryenSIMDShuffleGetMask"

# 'SIMDBitselect' expression operations
export_function "_BinaryenSIMDBitselectGetLeft"
export_function "_BinaryenSIMDBitselectGetRight"
export_function "_BinaryenSIMDBitselectGetCond"

# 'SIMDShift' expression operations
export_function "_BinaryenSIMDShiftGetOp"
export_function "_BinaryenSIMDShiftGetVec"
export_function "_BinaryenSIMDShiftGetShift"

# 'Module' operations
export_function "_BinaryenModuleCreate"
export_function "_BinaryenModuleDispose"
Expand Down
143 changes: 142 additions & 1 deletion scripts/gen-s-parser.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -268,6 +268,147 @@
("i64.trunc_u:sat/f32", "makeUnary(s, UnaryOp::TruncSatUFloat32ToInt64)"),
("i64.trunc_s:sat/f64", "makeUnary(s, UnaryOp::TruncSatSFloat64ToInt64)"),
("i64.trunc_u:sat/f64", "makeUnary(s, UnaryOp::TruncSatUFloat64ToInt64)"),
# SIMD ops
("v128.load", "makeLoad(s, v128, /*isAtomic=*/false)"),
("v128.store", "makeStore(s, v128, /*isAtomic=*/false)"),
("v128.const", "makeConst(s, v128)"),
("v8x16.shuffle", "makeSIMDShuffle(s)"),
("i8x16.splat", "makeUnary(s, UnaryOp::SplatVecI8x16)"),
("i8x16.extract_lane_s", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneSVecI8x16, 16)"),
("i8x16.extract_lane_u", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneUVecI8x16, 16)"),
("i8x16.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI8x16, 16)"),
("i16x8.splat", "makeUnary(s, UnaryOp::SplatVecI16x8)"),
("i16x8.extract_lane_s", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneSVecI16x8, 8)"),
("i16x8.extract_lane_u", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneUVecI16x8, 8)"),
("i16x8.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8)"),
("i32x4.splat", "makeUnary(s, UnaryOp::SplatVecI32x4)"),
("i32x4.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecI32x4, 4)"),
("i32x4.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI32x4, 4)"),
("i64x2.splat", "makeUnary(s, UnaryOp::SplatVecI64x2)"),
("i64x2.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecI64x2, 2)"),
("i64x2.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI64x2, 2)"),
("f32x4.splat", "makeUnary(s, UnaryOp::SplatVecF32x4)"),
("f32x4.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecF32x4, 4)"),
("f32x4.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecF32x4, 4)"),
("f64x2.splat", "makeUnary(s, UnaryOp::SplatVecF64x2)"),
("f64x2.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecF64x2, 2)"),
("f64x2.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecF64x2, 2)"),
("i8x16.eq", "makeBinary(s, BinaryOp::EqVecI8x16)"),
("i8x16.ne", "makeBinary(s, BinaryOp::NeVecI8x16)"),
("i8x16.lt_s", "makeBinary(s, BinaryOp::LtSVecI8x16)"),
("i8x16.lt_u", "makeBinary(s, BinaryOp::LtUVecI8x16)"),
("i8x16.gt_s", "makeBinary(s, BinaryOp::GtSVecI8x16)"),
("i8x16.gt_u", "makeBinary(s, BinaryOp::GtUVecI8x16)"),
("i8x16.le_s", "makeBinary(s, BinaryOp::LeSVecI8x16)"),
("i8x16.le_u", "makeBinary(s, BinaryOp::LeUVecI8x16)"),
("i8x16.ge_s", "makeBinary(s, BinaryOp::GeSVecI8x16)"),
("i8x16.ge_u", "makeBinary(s, BinaryOp::GeUVecI8x16)"),
("i16x8.eq", "makeBinary(s, BinaryOp::EqVecI16x8)"),
("i16x8.ne", "makeBinary(s, BinaryOp::NeVecI16x8)"),
("i16x8.lt_s", "makeBinary(s, BinaryOp::LtSVecI16x8)"),
("i16x8.lt_u", "makeBinary(s, BinaryOp::LtUVecI16x8)"),
("i16x8.gt_s", "makeBinary(s, BinaryOp::GtSVecI16x8)"),
("i16x8.gt_u", "makeBinary(s, BinaryOp::GtUVecI16x8)"),
("i16x8.le_s", "makeBinary(s, BinaryOp::LeSVecI16x8)"),
("i16x8.le_u", "makeBinary(s, BinaryOp::LeUVecI16x8)"),
("i16x8.ge_s", "makeBinary(s, BinaryOp::GeSVecI16x8)"),
("i16x8.ge_u", "makeBinary(s, BinaryOp::GeUVecI16x8)"),
("i32x4.eq", "makeBinary(s, BinaryOp::EqVecI32x4)"),
("i32x4.ne", "makeBinary(s, BinaryOp::NeVecI32x4)"),
("i32x4.lt_s", "makeBinary(s, BinaryOp::LtSVecI32x4)"),
("i32x4.lt_u", "makeBinary(s, BinaryOp::LtUVecI32x4)"),
("i32x4.gt_s", "makeBinary(s, BinaryOp::GtSVecI32x4)"),
("i32x4.gt_u", "makeBinary(s, BinaryOp::GtUVecI32x4)"),
("i32x4.le_s", "makeBinary(s, BinaryOp::LeSVecI32x4)"),
("i32x4.le_u", "makeBinary(s, BinaryOp::LeUVecI32x4)"),
("i32x4.ge_s", "makeBinary(s, BinaryOp::GeSVecI32x4)"),
("i32x4.ge_u", "makeBinary(s, BinaryOp::GeUVecI32x4)"),
("f32x4.eq", "makeBinary(s, BinaryOp::EqVecF32x4)"),
("f32x4.ne", "makeBinary(s, BinaryOp::NeVecF32x4)"),
("f32x4.lt", "makeBinary(s, BinaryOp::LtVecF32x4)"),
("f32x4.gt", "makeBinary(s, BinaryOp::GtVecF32x4)"),
("f32x4.le", "makeBinary(s, BinaryOp::LeVecF32x4)"),
("f32x4.ge", "makeBinary(s, BinaryOp::GeVecF32x4)"),
("f64x2.eq", "makeBinary(s, BinaryOp::EqVecF64x2)"),
("f64x2.ne", "makeBinary(s, BinaryOp::NeVecF64x2)"),
("f64x2.lt", "makeBinary(s, BinaryOp::LtVecF64x2)"),
("f64x2.gt", "makeBinary(s, BinaryOp::GtVecF64x2)"),
("f64x2.le", "makeBinary(s, BinaryOp::LeVecF64x2)"),
("f64x2.ge", "makeBinary(s, BinaryOp::GeVecF64x2)"),
("v128.not", "makeUnary(s, UnaryOp::NotVec128)"),
("v128.and", "makeBinary(s, BinaryOp::AndVec128)"),
("v128.or", "makeBinary(s, BinaryOp::OrVec128)"),
("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"),
("v128.bitselect", "makeSIMDBitselect(s)"),
("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"),
("i8x16.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI8x16)"),
("i8x16.all_true", "makeUnary(s, UnaryOp::AllTrueVecI8x16)"),
("i8x16.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI8x16)"),
("i8x16.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI8x16)"),
("i8x16.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI8x16)"),
("i8x16.add", "makeBinary(s, BinaryOp::AddVecI8x16)"),
("i8x16.add_saturate_s", "makeBinary(s, BinaryOp::AddSatSVecI8x16)"),
("i8x16.add_saturate_u", "makeBinary(s, BinaryOp::AddSatUVecI8x16)"),
("i8x16.sub", "makeBinary(s, BinaryOp::SubVecI8x16)"),
("i8x16.sub_saturate_s", "makeBinary(s, BinaryOp::SubSatSVecI8x16)"),
("i8x16.sub_saturate_u", "makeBinary(s, BinaryOp::SubSatUVecI8x16)"),
("i8x16.mul", "makeBinary(s, BinaryOp::MulVecI8x16)"),
("i16x8.neg", "makeUnary(s, UnaryOp::NegVecI16x8)"),
("i16x8.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI16x8)"),
("i16x8.all_true", "makeUnary(s, UnaryOp::AllTrueVecI16x8)"),
("i16x8.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI16x8)"),
("i16x8.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI16x8)"),
("i16x8.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI16x8)"),
("i16x8.add", "makeBinary(s, BinaryOp::AddVecI16x8)"),
("i16x8.add_saturate_s", "makeBinary(s, BinaryOp::AddSatSVecI16x8)"),
("i16x8.add_saturate_u", "makeBinary(s, BinaryOp::AddSatUVecI16x8)"),
("i16x8.sub", "makeBinary(s, BinaryOp::SubVecI16x8)"),
("i16x8.sub_saturate_s", "makeBinary(s, BinaryOp::SubSatSVecI16x8)"),
("i16x8.sub_saturate_u", "makeBinary(s, BinaryOp::SubSatUVecI16x8)"),
("i16x8.mul", "makeBinary(s, BinaryOp::MulVecI16x8)"),
("i32x4.neg", "makeUnary(s, UnaryOp::NegVecI32x4)"),
("i32x4.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI32x4)"),
("i32x4.all_true", "makeUnary(s, UnaryOp::AllTrueVecI32x4)"),
("i32x4.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI32x4)"),
("i32x4.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI32x4)"),
("i32x4.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI32x4)"),
("i32x4.add", "makeBinary(s, BinaryOp::AddVecI32x4)"),
("i32x4.sub", "makeBinary(s, BinaryOp::SubVecI32x4)"),
("i32x4.mul", "makeBinary(s, BinaryOp::MulVecI32x4)"),
("i64x2.neg", "makeUnary(s, UnaryOp::NegVecI64x2)"),
("i64x2.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI64x2)"),
("i64x2.all_true", "makeUnary(s, UnaryOp::AllTrueVecI64x2)"),
("i64x2.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI64x2)"),
("i64x2.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI64x2)"),
("i64x2.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI64x2)"),
("i64x2.add", "makeBinary(s, BinaryOp::AddVecI64x2)"),
("i64x2.sub", "makeBinary(s, BinaryOp::SubVecI64x2)"),
("f32x4.abs", "makeUnary(s, UnaryOp::AbsVecF32x4)"),
("f32x4.neg", "makeUnary(s, UnaryOp::NegVecF32x4)"),
("f32x4.sqrt", "makeUnary(s, UnaryOp::SqrtVecF32x4)"),
("f32x4.add", "makeBinary(s, BinaryOp::AddVecF32x4)"),
("f32x4.sub", "makeBinary(s, BinaryOp::SubVecF32x4)"),
("f32x4.mul", "makeBinary(s, BinaryOp::MulVecF32x4)"),
("f32x4.div", "makeBinary(s, BinaryOp::DivVecF32x4)"),
("f32x4.min", "makeBinary(s, BinaryOp::MinVecF32x4)"),
("f32x4.max", "makeBinary(s, BinaryOp::MaxVecF32x4)"),
("f64x2.abs", "makeUnary(s, UnaryOp::AbsVecF64x2)"),
("f64x2.neg", "makeUnary(s, UnaryOp::NegVecF64x2)"),
("f64x2.sqrt", "makeUnary(s, UnaryOp::SqrtVecF64x2)"),
("f64x2.add", "makeBinary(s, BinaryOp::AddVecF64x2)"),
("f64x2.sub", "makeBinary(s, BinaryOp::SubVecF64x2)"),
("f64x2.mul", "makeBinary(s, BinaryOp::MulVecF64x2)"),
("f64x2.div", "makeBinary(s, BinaryOp::DivVecF64x2)"),
("f64x2.min", "makeBinary(s, BinaryOp::MinVecF64x2)"),
("f64x2.max", "makeBinary(s, BinaryOp::MaxVecF64x2)"),
("i32x4.trunc_s/f32x4:sat", "makeUnary(s, UnaryOp::TruncSatSVecF32x4ToVecI32x4)"),
("i32x4.trunc_u/f32x4:sat", "makeUnary(s, UnaryOp::TruncSatUVecF32x4ToVecI32x4)"),
("i64x2.trunc_s/f64x2:sat", "makeUnary(s, UnaryOp::TruncSatSVecF64x2ToVecI64x2)"),
("i64x2.trunc_u/f64x2:sat", "makeUnary(s, UnaryOp::TruncSatUVecF64x2ToVecI64x2)"),
("f32x4.convert_s/i32x4", "makeUnary(s, UnaryOp::ConvertSVecI32x4ToVecF32x4)"),
("f32x4.convert_u/i32x4", "makeUnary(s, UnaryOp::ConvertUVecI32x4ToVecF32x4)"),
("f64x2.convert_s/i64x2", "makeUnary(s, UnaryOp::ConvertSVecI64x2ToVecF64x2)"),
("f64x2.convert_u/i64x2", "makeUnary(s, UnaryOp::ConvertUVecI64x2ToVecF64x2)")
]


Expand Down Expand Up @@ -308,7 +449,7 @@ def _common_prefix(a, b):

def do_insert(self, full_inst, inst, expr):
if inst is "":
assert self.expr is None, "Repeated instruction"
assert self.expr is None, "Repeated instruction " + full_inst
self.expr = expr
self.inst = full_inst
return
Expand Down
Loading