DSPi Firmware v1.1.2b
RP2350/2040: Removed SPDIF consumer pool buffer prefill to address issue #29
RP2350/2040: Added comprehensive SPDIF consumer pool statistics
RP2350/2040: Raised base system clock to 307.2MHz to achieve integer PIO divider for I2S and SPDIF
RP2350: Raised base voltage to 1.15V to ensure stability at new base clock.