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@akumanatt
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This update adds 2 write bits to VERA registers: AUDIO_CTRL bit 6 and AUDIO_RATE bit 7.

Writing 1 to AUDIO_CTRL bit 6 will only reset FIFO's read position to 0. This allows a sample data in the buffer to be replayed any time without refilling it again. AUDIO_RATE bit 7 set will enable looped playback where the read position is automatically reset to 0 if the buffer becomes empty in the next sample. Although an AUDIO_RATE value of 128 will still play at the maximum rate without looping.

Note that a position of 0 here means an internal buffer's address. Which means a FIFO reset (write 1 to AUDIO_CTRL bit 7) is required in order to reset the write position to 0 too before uploading a sample data and make these methods above play correctly.

@visual-trials
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I have tried to include these changes into the fx-branch. After doing so I found out a few things:

  • The change raised the LUT count by 46, which is more than you would expect.
  • Attempts to reduce the LUT-count were partially successful (down to 16 LUTs) but resulted in a different way of interfacing with the looping/reset settings, which may be undesired.
  • The change resets rdidx_r (in audio_fifo.v) when a restart of the read position is triggered. However, the state_r (in pcm.v) is not reset. This means that the fifo-reading might be in an intermediate state (say: 8-bit stereo, and only the left byte has been read, but not the right one) when the fifo read position is reset. This may cause strange/unwanted effects.
  • It is probably required to wait for the state to be DONE or IDLE before executing a read-reset. This means some logic needs to be added and/or adjusted.

It is probably prudent to re-think how the logic should work and how the interface should work for this feature. Then implement that. Then LUT-optimization (and review) can be performed.

JeffreyH

jburks pushed a commit that referenced this pull request Jul 23, 2023
@akumanatt
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I updated the loop method to be a combination of AUDIO_CTRL bits 6-7 now. Also, I made it reset only in IDLE state.

@mooinglemur mooinglemur merged commit 70a03e0 into X16Community:main Aug 12, 2023
mooinglemur added a commit that referenced this pull request Aug 12, 2023
@mooinglemur
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I accidentally merged this one. If we need to revert, we can merge #19

mooinglemur pushed a commit to mooinglemur/vera-module that referenced this pull request Aug 14, 2023
* Add an ability to replay and loop FIFO data

* Change FIFO loop method and only restart on sample word boundary
mooinglemur added a commit that referenced this pull request Sep 16, 2023
This reverts commit 70a03e0.

Was accidentally merged in.
@mooinglemur
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This merge has been reverted after discussions on Discord. JeffreyH has some concerns about potential timing problems in this implementation that might unfortunately be costly in LUTs to fix, and it blocks the potential merge of fx into main. Please rework this feature against the fx branch and open a new PR.

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3 participants