aie_dtrace VE2 CT writer: fix peak_*_bandwidth SS port programming#79
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For peak_read_bandwidth and peak_write_bandwidth, generateStreamSwitchPortConfig
indexed the Stream_Switch_Event_Port_Selection_0 logical SS slots by counter
number (0..3), so the per-counter list {Ch0, Ch0, Ch1, Ch1} was placed into
slots 0..3. The four perf counters for these metrics use events Port_Running_0,
Port_Stalled_0, Port_Running_1 and Port_Stalled_1, which only read logical SS
ports 0 and 1 - so Counter 2/3 ended up sampling the Ch0 programming on slot
1, and the Ch1 programming on slots 2/3 was never read by any counter.
Pack only the unique configs into the SS slots that the perf counter events
reference. For peak metrics, slot 0 = configs[0] (channel 0) and slot 1 =
configs[2] (channel 1); slots 2 and 3 are left zero. ddr_bandwidth,
read_bandwidth and write_bandwidth still use 4 distinct logical SS ports and
keep the existing 1:1 mapping. Per-counter metadata and PerfCtrl0/2 register
writes are unchanged.
After this fix, the SS port write becomes 0x00000905 for peak_read_bandwidth
and 0x00002523 for peak_write_bandwidth (vs 0x09090505 / 0x25252323 before),
so Counter 2/3 now correctly monitor channel 1.
Co-authored-by: Cursor <cursoragent@cursor.com>
jvillarre
approved these changes
Jun 3, 2026
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For peak_read_bandwidth and peak_write_bandwidth, generateStreamSwitchPortConfig indexed the Stream_Switch_Event_Port_Selection_0 logical SS slots by counter number (0..3), so the per-counter list {Ch0, Ch0, Ch1, Ch1} was placed into slots 0..3. The four perf counters for these metrics use events Port_Running_0, Port_Stalled_0, Port_Running_1 and Port_Stalled_1, which only read logical SS ports 0 and 1 - so Counter 2/3 ended up sampling the Ch0 programming on slot 1, and the Ch1 programming on slots 2/3 was never read by any counter.
Pack only the unique configs into the SS slots that the perf counter events reference. For peak metrics, slot 0 = configs[0] (channel 0) and slot 1 = configs[2] (channel 1); slots 2 and 3 are left zero. ddr_bandwidth, read_bandwidth and write_bandwidth still use 4 distinct logical SS ports and keep the existing 1:1 mapping. Per-counter metadata and PerfCtrl0/2 register writes are unchanged.
After this fix, the SS port write becomes 0x00000905 for peak_read_bandwidth and 0x00002523 for peak_write_bandwidth (vs 0x09090505 / 0x25252323 before), so Counter 2/3 now correctly monitor channel 1.