updating the PL xclbin check to align with latest Vitis TA#9688
Merged
chvamshi-xilinx merged 1 commit intoXilinx:masterfrom Mar 23, 2026
Merged
updating the PL xclbin check to align with latest Vitis TA#9688chvamshi-xilinx merged 1 commit intoXilinx:masterfrom
chvamshi-xilinx merged 1 commit intoXilinx:masterfrom
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Signed-off-by: Bikash Singha <bisingha@xcobisingha50x.amd.com>
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clang-tidy review says "All clean, LGTM! 👍" |
chvamshi-xilinx
approved these changes
Mar 23, 2026
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Problem solved by the commit
https://jira.xilinx.com/browse/CR-1263883
Bug / issue (if any) fixed, which PR introduced the bug, how it was discovered
With latest 2026.1 Vitis TA, IP_LAYOUT section is being packaged to all the xclbins. So distinguishing based on IP_LAYOUT section for PL xclbins is no longer valid. Updated the check to align with latest TA.
How problem was solved, alternative solutions (if any) and why they were rejected
Problem was solved by adding proper check to correctly distinguish the PL and AIE only xclbins. So, for PL xclbin goes to slot 0 as expected and AIE only xclbins are assigned a dynamic slot (eg: 0, 1, 2, ..)
Risks (if any) associated the changes in the commit
n/a
What has been tested and how, request additional testing if necessary
I've tested multiple usecases and all the tests are passing.
pl_onlyxclbin via hw_context, then loadaie_onlyxclbin via hw_context -- second load succeeds on a dynamic slotDocumentation impact (if any)
n/a