Release of FINN v1.0.0-alpha

[auphelia]

FINN v1.0.0-alpha — Release Notes

Alpha of the FINN v1 line. This release lands major architectural capabilities for v1. It is just the beginning, with more features and hardening to come.

We encourage you to try FINN v1-alpha and put it to use. We welcome your feedback and contributions via GitHub issues and discussions.

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1. Foundational support for attention-based models (Transformers)

The core building blocks for compiling attention/transformer networks are in place, making BERT-class models targetable. End-to-end hardening continues into beta.

New and considerably generalized operators

🤖 Transformer-related

• Softmax (RTL + HLS)
• LayerNorm (RTL + HLS)
• Dynamic MatMul
• Shuffle
• PWPolyF (piecewise-polynomial activation)
• Where
• Pad1d
• SelectToken
• Crop
• Scaled Dot-Product Attention streamlining
• Generic elementwise/residual paths

⚙️ General-purpose additions and enhancements

• Split
• Concat (updated)
• Elementwise Binary (HLS + RTL) — generic binary elementwise
• Upsampler — generalized Bresenham-based nearest-neighbour upsampling
• Rectangular Downsampler — implemented via the RTL ConvolutionInputGenerator
• Pool — MaxPool is now consolidated into a single unified layer
• Elementwise operators and Thresholding — added fixed-point and floating-point support
• Pumped compute for MVAUs and pumped memory for internal_decoupled mode
• Arbitrary-precision DSP-packed MVAUs — no longer restricted to 4-bit/8-bit

⚠️ Migration note: MaxPool is no longer specialized to a separate StreamingMaxPool layer. It is now inferred as the unified Pool (pool_hls) layer. Update any folding configurations or scripts that reference StreamingMaxPool node names to use the new Pool layer.

Architectural capabilities enabling larger models

• Floating-point support (FP32/FP16): needed both to implement Softmax and LayerNorm and to mitigate streamlining limitations. Paths that cannot be fully streamlined to integer arithmetic can now remain in floating point.
• Multi-Layer Offload (MLO) + FINNLoop: a new loop-rolling architecture that time-shares one hardware instance across repeated structures, such as transformer encoder layers, instead of unrolling per layer.
• Weight tiling and external (DDR) weights: large weight tensors that no longer fit on-chip are tiled and streamed from external DDR memory on demand. Together with MLO, this is what makes large/deep models buildable.

2. Improvements on ease of use

A concerted usability push across building, extending, and debugging FINN.

• Builder Phase Architecture — the build pipeline is now organized into explicit phases.
• HW-conversion validation pass — a new analysis pass reports why a model (or specific node) was not converted to hardware, plus up-front reporting of invalid custom-op configs, instead of failing deep into a long build.
• Custom-op authoring cleanups — much less boilerplate to define a new op:
  • unified kernel interface (in0_V, in1_V, … / out0_V, out1_V, …),
  • shared logic moved into parent classes (fewer functions to implement),
  • new HLS node attributes cpp_interface (hls packed / hls vector) and hls_style (freerunning / fm aware).
• New documentation on creating custom ops (customop-pattern, updated developer guide), plus auto-generated PDF documentation from ReadTheDocs.
• Local, Docker-less install option for running FINN without the container.
• New RTL simulation stack (finnxsi) — replaces pyverilator with a ground-up backend: node-by-node waveform capture, FIFO tracing, and robust watchdog/timeout handling.
• Consolidated general FIFO implementation - replaces the previous convoluted logic to satisfy the needs of FINN designs by composing from different external FIFO solutions.

3. Move to Vivado 2024.2

Moving the default flow onto a current toolchain and current silicon.

• Stable Vivado/Vitis 2024.2 support, with 2025.1 and 2025.2 also tested and usable.
• Updated XRT to the 2024.2 release.
• Retired boards: U280 and Pynq-Z1/Z2 support is removed, replaced by U55C and AUP-ZU3 — see the announcement: Board and tool version updates coming to FINN #1663.
• New silicon: AUP-ZU3 bring-up (via ZynqBuild) and Versal V80 (built via the new SLASH flow using the slashkit linker); DSP58 (Versal) is leveraged for compute, in particular for efficient floating-point compute.

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Additional improvements

FINN builder flow

Changes across the build pipeline, simulation, streamlining, and deployment:

• FIFO sizing: simulation-based sizing with a queue-based unbounded FIFO drop-in, input throttling, waveform saving, and a user-configurable number of inferences fed to the sizing sim (default 2); plus behavioural models for RTL layers during FIFO sim.
• Builder: node-by-node rtlsim, transpose decomposition, and ApplyConfig moved into FINN (from qonnx).
• Streamlining: new transformations for branching structures, and threshold flooring/clipping enabled later in the flow (on Thresholding layers, not just MultiThreshold).
• Deployment: C++ driver as an alternative to the PYNQ driver for Alveo cards.

Other changes

Many additional fixes and smaller improvements are included.

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Acknowledgements

This release reflects the work of many contributors across AMD, the FINN team, and the wider community. Thanks to everyone who contributed features, fixes, and reviews (listed alphabetically by username, not by contribution):

@alexhornburg-xlnx · @bwintermann · @d-kor · @fpjentzsch · @hannahxy13 · @iksnagreb · @jmonks-amd · @JOOpdenhoevel · @jsmonson · @klassen9 · @LeahLS · @LinusJungemann · @liuzrcc · @lstasytis · @maltanar · @mdanilow · @merkelmarrow · @mrontio · @ollycassidy13 · @preusser · @rothej · @senekor · @sgerber-amd ·
@shashwat1198 · @SpiritSeeker · @STFleming · @tafk7

See the full contributor list at https://github.com/Xilinx/finn/blob/main/AUTHORS.rst.

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