Replies: 3 comments 4 replies
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Thanks for this writeup! The more work we can shift away from Chess will greatly reduce runner load, we can execute more in parallel as Chess is the real resource hog. For the questions:
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For the sake of patching together previous work:
I don't think either of them are being worked on at the moment, but they may provide some useful information. |
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@atassis I'd just like to express to you my sincere gratitude that you are taking this up. It does not look like an easy task, but it is one that I think will bear great fruit. |
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Follow-up to #3405, which @hunhoffe asked me to open. The direction reads as settled on that thread:
Peano is the future, and the thing actually anchoring Chess is
aiesim(the ISS), not the compiler. Sothis is a scoping of what the migration takes, where that anchor really sits, and an offer to help with
both halves.
The Chess dependency in the test suite is really two different things, and separating them is the whole
point:
xchesscc), andxca_udm_dbg/aiesimulator).The compiler half is tractable engineering on the open backend. The simulator is the one piece that is
genuinely Chess-only. Numbers grepped from
upstream/main(correct me if my greps are loose):xchesscc; 68 already carry--no-xchesscc(Peano).xca_udm_dbg/aiesimulator); 20 of those are gatedREQUIRES: aiesimulator, valid_xchess_license. 74 files carryREQUIRES: valid_xchess_licenseoverall.PEANO-NOTtests, 1chess_storageuse intest/(6 more live in
programming_examples), and noUNSUPPORTED: peanomarkers (though Peano-incompat isreally tracked through the 74 license markers, not that one, so 0 there is not evidence of readiness).
The compiler half
The docs already say you can skip Vitis and target AIE2/AIE2P with Peano, and the
ml/normexample runs onPeano today. For a Chess-compile test that already has a device run, migration is a flag swap plus running
on the NPU; for the compile/IR unit tests it is a flag swap with no device at all. The honest caveats: real
gaps exist right now (the repo's own
block_datatypesREADME notes Peano's AIE2P backend still crashes onthe bfp16 matmul kernels), and Chess-vs-Peano codegen quality is its own open question. Each gap is a filed
llvm-aie fix, which is the backend area I am already working in.
The simulator half, and it is the real work
About 61 tests do functional numeric verification inside the Chess ISS, hardware-free. I piloted the aievec
bf16_*family (test/unit_tests/aievec_tests/aie2/): thetestbench.ccthere is a host program (it usesfopen/fprintfto read and write data files) that runs in the simulator. So flipping these is not aRUN-line edit, it is a per-test execution-model rewrite that moves the numeric check from the ISS to the
device. That, not the compiler, is where the cost sits.
The tradeoff to name up front, because it is exactly #3405's concern
Those ~61 ISS tests run today with no NPU. Moving them to device verification shifts their load onto the
same scarce device runners #3405 is about. So the pragmatic near-term is to keep Chess for the ISS and
migrate the compiler side, which removes the Vitis requirement from most tests and the Chess-specific
serialization without adding device load.
The keystone, then, is
aiesimitself. It is the one piece with no open replacement today, it is what tiesthe remaining tests to Vitis, and porting it off that dependency is what would let those tests stay
hardware-free instead of moving onto the runners. I would be glad to help port or reimplement that
hardware-free verification path, and I would rather do it with a working slice than argue it in the
abstract. Functional numeric checks are the tractable part; a native cost model for cycle-level timing is a
separate and harder question I would not want to hand-wave. If that is a direction worth opening, I am happy
to take a first cut and report what the open path can actually reach.
Suggested shape, gradual and reversible
runner load tracked so it does not surprise anyone.
chess_storage, any compile failures) as filed llvm-aieissues.
as-is), so the Vitis dependency becomes optional rather than removed.
Two questions, to size this against constraints I cannot see:
the device-runner cost that shift carries? Or is the hardware-free ISS coverage something to keep exactly
as it is for now?
anyone commits to the sim-test conversion?
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