Rename CPUOptions to CPU_Options

core/src/cpus/cortex_m.zig

@@ -30,7 +30,7 @@ pub const InterruptOptions = microzig.utilities.GenerateInterruptOptions(&.{
 });
 
 /// Allowable `platform` options for microzig.options.
-pub const CPUOptions = core.CPUOptions;
+pub const CPU_Options = core.CPU_Options;
 
 /// External Interrupts
 /// These are the interrupts generated by the NVIC.

core/src/cpus/cortex_m/m0.zig

@@ -1,7 +1,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {};
+pub const CPU_Options = struct {};
 
 pub const scb_base_offset = 0x0d00;
 

core/src/cpus/cortex_m/m0plus.zig

@@ -1,7 +1,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/cpus/cortex_m/m3.zig

@@ -1,7 +1,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/cpus/cortex_m/m33.zig

@@ -3,7 +3,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/cpus/cortex_m/m4.zig

@@ -1,7 +1,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/cpus/cortex_m/m55.zig

@@ -3,7 +3,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/cpus/cortex_m/m7.zig

@@ -1,7 +1,7 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     /// When true, interrupt vectors are moved to RAM so handlers can be set at runtime.
     ram_vectors: bool = false,
     /// When true, the RAM vectors are placed in section `ram_vectors`.

core/src/microzig.zig

@@ -63,7 +63,7 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu
 
 pub const InterruptOptions = if (@hasDecl(cpu, "InterruptOptions")) cpu.InterruptOptions else struct {};
 
-pub const CPUOptions = if (@hasDecl(cpu, "CPUOptions")) cpu.CPUOptions else struct {};
+pub const CPU_Options = if (@hasDecl(cpu, "CPU_Options")) cpu.CPU_Options else struct {};
 
 pub const Options = struct {
     log_level: std.log.Level = std.log.default_level,
@@ -87,7 +87,7 @@ pub const Options = struct {
         }
     }.log,
     interrupts: InterruptOptions = .{},
-    cpu: CPUOptions = .{},
+    cpu: CPU_Options = .{},
 };
 
 /// Hangs the processor and will stop doing anything useful. Use with caution!

port/raspberrypi/rp2xxx/src/cpus/hazard3.zig

@@ -4,7 +4,7 @@ const microzig_options = root.microzig_options;
 const microzig = @import("microzig");
 const riscv32_common = @import("riscv32-common");
 
-pub const CPUOptions = struct {
+pub const CPU_Options = struct {
     ram_vectors: bool = true,
     has_ram_vectors_section: bool = false,
 };