esp: join cpu and add rom functions

port/espressif/esp/build.zig

@@ -15,13 +15,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
     const b = dep.builder;
 
     const riscv32_common_dep = b.dependency("microzig/modules/riscv32-common", .{});
-
-    const cpu_imports: []Import = b.allocator.dupe(Import, &.{
-        .{
-            .name = "riscv32-common",
-            .module = riscv32_common_dep.module("riscv32-common"),
-        },
-    }) catch @panic("OOM");
+    const riscv32_common_mod = riscv32_common_dep.module("riscv32-common");
 
     const hal: microzig.HardwareAbstractionLayer = .{
         .root_source_file = b.path("src/hal.zig"),
@@ -47,8 +41,17 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .cpu = .{
             .name = "esp_riscv",
-            .root_source_file = b.path("src/cpus/esp_riscv_image_boot.zig"),
-            .imports = cpu_imports,
+            .root_source_file = b.path("src/cpus/esp_riscv.zig"),
+            .imports = b.allocator.dupe(Import, &.{
+                .{
+                    .name = "cpu-config",
+                    .module = get_cpu_config(b, .image),
+                },
+                .{
+                    .name = "riscv32-common",
+                    .module = riscv32_common_mod,
+                },
+            }) catch @panic("OOM"),
         },
         .chip = .{
             .name = "ESP32-C3",
@@ -62,7 +65,12 @@ pub fn init(dep: *std.Build.Dependency) Self {
             },
         },
         .hal = hal,
-        .linker_script = b.path("esp32_c3.ld"),
+        .linker_script = generate_linker_script(
+            dep,
+            "esp32_c3.ld",
+            b.path("ld/esp32_c3/esp32_c3.ld.base"),
+            b.path("ld/esp32_c3/rom_functions.ld"),
+        ),
     };
 
     return .{
@@ -72,10 +80,24 @@ pub fn init(dep: *std.Build.Dependency) Self {
                 .preferred_binary_format = .bin,
                 .cpu = .{
                     .name = "esp_riscv",
-                    .root_source_file = b.path("src/cpus/esp_riscv_direct_boot.zig"),
-                    .imports = cpu_imports,
+                    .root_source_file = b.path("src/cpus/esp_riscv.zig"),
+                    .imports = b.allocator.dupe(Import, &.{
+                        .{
+                            .name = "cpu-config",
+                            .module = get_cpu_config(b, .direct),
+                        },
+                        .{
+                            .name = "riscv32-common",
+                            .module = riscv32_common_mod,
+                        },
+                    }) catch @panic("OOM"),
                 },
-                .linker_script = b.path("esp32_c3_direct_boot.ld"),
+                .linker_script = generate_linker_script(
+                    dep,
+                    "esp32_c3_direct_boot.ld",
+                    b.path("ld/esp32_c3/esp32_c3_direct_boot.ld.base"),
+                    b.path("ld/esp32_c3/rom_functions.ld"),
+                ),
             }),
         },
         .boards = .{},
@@ -93,4 +115,42 @@ pub fn build(b: *std.Build) void {
     const unit_tests_run = b.addRunArtifact(unit_tests);
     const test_step = b.step("test", "Run platform agnostic unit tests");
     test_step.dependOn(&unit_tests_run.step);
+
+    const cat_exe = b.addExecutable(.{
+        .name = "cat",
+        .root_module = b.createModule(.{
+            .root_source_file = b.path("src/tools/cat.zig"),
+            .target = b.graph.host,
+            .optimize = .ReleaseSafe,
+        }),
+    });
+    b.installArtifact(cat_exe);
+}
+
+const BootMode = enum {
+    direct,
+    image,
+};
+
+fn get_cpu_config(b: *std.Build, boot_mode: BootMode) *std.Build.Module {
+    const options = b.addOptions();
+    options.addOption(BootMode, "boot_mode", boot_mode);
+    return b.createModule(.{
+        .root_source_file = options.getOutput(),
+    });
+}
+
+fn generate_linker_script(
+    dep: *std.Build.Dependency,
+    output_name: []const u8,
+    base_path: std.Build.LazyPath,
+    rom_functions_path: std.Build.LazyPath,
+) std.Build.LazyPath {
+    const b = dep.builder;
+    const cat_exe = dep.artifact("cat");
+
+    const run = b.addRunArtifact(cat_exe);
+    run.addFileArg(base_path);
+    run.addFileArg(rom_functions_path);
+    return run.addOutputFileArg(output_name);
 }

port/espressif/esp/ld/esp32_c3/esp32_c3.ld.base

@@ -0,0 +1,86 @@
+ENTRY(_start);
+
+MEMORY
+{
+    irom (rx) : ORIGIN = 0x42000020, LENGTH = 0x800000 - 0x20
+    drom (r) : ORIGIN = 0x3C000020, LENGTH = 0x800000 - 0x20
+
+    /* Offset by ICache size which is fixed to 16KB on ESP32-C3 */
+    iram (rwx) : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 313K
+    dram (rw) : ORIGIN = 0x3FC7C000 + 0x4000, LENGTH = 313K
+}
+
+SECTIONS
+{
+    .irom.text :
+    {
+        microzig_text_start = .;
+
+        KEEP(*(microzig_flash_start))
+        *(.text*)
+
+        microzig_text_end = .;
+
+        /**
+         * CPU will try to prefetch up to 16 bytes of of instructions.
+         * This means that any configuration (e.g. MMU, PMS) must allow
+         * safe access to up to 16 bytes after the last real instruction, add
+         * dummy bytes to ensure this
+         */
+        . += 16;
+    } > irom
+
+    .drom.dummy (NOLOAD) :
+    {
+        . = ORIGIN(drom) + (microzig_text_end - microzig_text_start);
+
+        /* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
+        . = ALIGN(0x10000) + 0x20;
+    } > drom
+
+    .drom.rodata :
+    {
+        microzig_rodata_start = .;
+
+        KEEP(*(.app_desc))
+        *(.rodata*)
+
+        microzig_rodata_end = .;
+    } > drom
+
+    .iram.text :
+    {
+        microzig_rwtext_start = .;
+
+        KEEP(*(.trap))
+        *(.rwtext*)
+
+        microzig_rwtext_end = .;
+
+        /* TODO: in the case of memory protection there should be some alignment
+         * and offset done here (NOLOAD) */
+    } > iram
+
+    .dram.dummy (NOLOAD) :
+    {
+        . = ORIGIN(dram) + (microzig_rwtext_end - microzig_rwtext_start);
+    } > dram
+
+    .dram.data :
+    {
+        microzig_data_start = .;
+        *(.sdata*)
+        *(.data*)
+        microzig_data_end = .;
+    } > dram
+
+    .dram.bss (NOLOAD) :
+    {
+        microzig_bss_start = .;
+        *(.bss*)
+        *(.sbss*)
+        microzig_bss_end = .;
+    } > dram
+
+    PROVIDE(__global_pointer$ = microzig_data_start + 0x800);
+}